Journals in DBLP

IEEE Design & Test of Computers
2001, volume: 18, number: 4

1. Yervant Zorian
   Error-Free Products. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:2-0 [Journal]
   
2. Carl Pixley
   Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:4-5 [Journal]
   
3. Harry Foster
   Applied Boolean Equivalence Verification and RTL Static Sign-Off. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:6-15 [Journal]
   
4. Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham
   Practical Formal Verification in Microprocessor Design. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:16-25 [Journal]
   
5. Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham
   Design and Development Paradigm for Industrial Formal Verification CAD Tools. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:26-35 [Journal]
   
6. Serdar Tasiran, Kurt Keutzer
   Coverage Metrics for Functional Validation of Hardware Designs. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:36-45 [Journal]
   
7. Lionel Bening, Harry Foster
   Optimizing Multiple EDA Tools within the ASIC Design Flow. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:46-55 [Journal]
   
8. Roberto d'Amore, Osamu Saotome, Karl Heinz Kienitz
   A Two-Input, One-Output Bit-Scalable Architecture for Fuzzy Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:56-64 [Journal]
   
9. 
   Roundtable: Adding Reconfigurable Logic to SOC Designs. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2001, v:18, n:4, pp:65-71 [Journal]
   
10. 
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:72-0 [Journal]
    
11. 
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:73-76 [Journal]
    
12. 
    DATC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:77-0 [Journal]
    
13. 
    TTCC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:78-79 [Journal]
    
14. Todd M. Austin
    Design for Verification? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2001, v:18, n:4, pp:80- [Journal]