Journals in DBLP

IEEE Design & Test of Computers
2000, volume: 17, number: 4

1. 
   D&T Elevated to Bimonthly. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:3-0 [Journal]
   
2. Magdy S. Abadir, Sumit DasGupta
   Guest Editors' Introduction: Microprocessor Test and Verification. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:4-5 [Journal]
   
3. Wei-Cheng Lai, Angela Krstic, Kwang-Ting (Tim) Cheng
   Functionally Testable Path Delay Faults on a Microprocessor. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:6-14 [Journal]
   
4. Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian
   Power-/Energy Efficient BIST Schemes for Processor Data Paths. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:15-28 [Journal]
   
5. Alfred L. Crouch, Michael Mateja, Teresa L. McLaurin, John C. Potter, Dat Tran
   Test Development for a Third-Version ColdFire Microprocessor. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:29-37 [Journal]
   
6. Noppanunt Utamaphethai, R. D. (Shawn) Blanton, John Paul Shen
   Effectiveness of Microarchitecture Test Program Generation. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:38-49 [Journal]
   
7. David Van Campenhout, Trevor N. Mudge, John P. Hayes
   Collection and Analysis of Microprocessor Design Errors. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:51-60 [Journal]
   
8. Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham
   Validating PowerPC Microprocessor Custom Memories. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:61-76 [Journal]
   
9. Hemant G. Rotithor
   Postsilicon Validation Methodology for Microprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2000, v:17, n:4, pp:77-88 [Journal]
   
10. Subhasish Mitra, LaNae J. Avra, Edward J. McCluskey
    Efficient Multiplexer Synthesis Techniques. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:90-97 [Journal]
    
11. 
    A D&T Roundtable: Power Delivery and Distribution. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:98-102 [Journal]
    
12. 
    Standards. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:102-103 [Journal]
    
13. 
    Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:104-105 [Journal]
    
14. 
    TTTC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:106-107 [Journal]
    
15. 
    DATC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:108-0 [Journal]
    
16. 
    IEEE Design & Test of Computers 2000 Annual Index, Volume 17. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:109-117 [Journal]
    
17. Scott Davidson
    Testing in 2100. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:4, pp:119-120 [Journal]