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Journals in DBLP

IEEE Design & Test of Computers
2000, volume: 17, number: 2

  1. Yervant Zorian
    Embedded in this issue. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:5-6 [Journal]

  2. News. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:6-9 [Journal]
  3. Donatella Sciuto
    Guest Editor's Introduction: Design Tools for Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:11-13 [Journal]
  4. Marco Sgroi, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
    Formal Models for Embedded System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:14-27 [Journal]
  5. Frank Slomka, Matthias Dörfel, Ralf Münzenberger, Richard Hofmann
    Hardware/Software Codesign and Rapid Prototyping of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:28-38 [Journal]
  6. Margarida F. Jacome, Gustavo de Veciana
    Design Challenges for New Application-Specific Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:40-50 [Journal]
  7. Michael Eisenring, Lothar Thiele, Eckart Zitzler
    Conflicting Criteria in Embedded System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:51-59 [Journal]
  8. Alberto Allara, Massimo Bombana, William Fornaciari, Fabio Salice
    A Case Study in Design Space Exploration: The Tosca Environment Applied to a Telecommunication Link Controller. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:60-72 [Journal]
  9. Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino
    Increasing Energy Efficiency of Embedded Systems by Application-Specific Memory Hierarchy Generation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:74-85 [Journal]
  10. Keith A. Jenkins, James P. Eckhardt
    Measuring Jitter and Phase Error in Microprocessor Phase-Locked Loops. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:86-93 [Journal]
  11. Dilip K. Bhavsar
    Synchronizing the IEEE 1149.1 Test Access Port for Chip-Level Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:94-99 [Journal]
  12. Janardhan H. Satyanarayana, Keshab K. Parhi
    Power Estimation of Digital Data Paths Using HEAT. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:101-110 [Journal]
  13. Hendrawan Soeleman, Kaushik Roy, Tan-Li Chou
    Estimating Circuit Activity in Combinational CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:112-119 [Journal]

  14. A D&T Roundtable: Design Automation in a Subwavelength Worl. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:120-126 [Journal]

  15. Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:127-135 [Journal]

  16. Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:136-139 [Journal]

  17. DATC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:140-0 [Journal]

  18. TTTC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:141-0 [Journal]
  19. Mukund Modi
    SCC20 Reports on Recent Standards Activities. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:142-143 [Journal]

  20. In the Licensing Dungeon: CAD by the Minute. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2000, v:17, n:2, pp:143-144 [Journal]
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