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Journals in DBLP

IEEE Design & Test of Computers
2004, volume: 21, number: 3

  1. Rajesh Gupta
    From the EIC: The next EDA challenge - Design for manufacturability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:169-0 [Journal]
  2. Vishwani D. Agrawal
    1985 to 1987: My years with D&T. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:173-174 [Journal]
  3. Carol Stolicny, Mustapha Slamani, Fidel Muradali, Geir Eide, Mike Li
    ITC 2003 panels: Part 2. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:175-176 [Journal]
  4. Yervant Zorian, Dimitris Gizopoulos, Cary Vandenberg, Philippe Magarshack
    Guest Editors' Introduction: Design for Yield and Reliability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:177-182 [Journal]
  5. Juan Antonio Carballo, Sani R. Nassif
    Impact of Design-Manufacturing Interface on SoC Design Methodologies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:183-191 [Journal]
  6. Alessandra Nardi, Alberto L. Sangiovanni-Vincentelli
    Logic Synthesis for Manufacturability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:192-199 [Journal]
  7. Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian
    SoC Yield Optimization via an Embedded-Memory Test and Repair Infrastructure. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:200-207 [Journal]
  8. Davide Appello, Alessandra Fudoli, Katia Giarda, Vincenzo Tancorre, Emil Gizdarski, Ben Mathew
    Understanding Yield Losses in Logic Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:208-215 [Journal]
  9. Melvin A. Breuer, Sandeep K. Gupta, T. M. Mak
    Defect and Error Tolerance in the Presence of Massive Numbers of Defects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:216-227 [Journal]
  10. Subhasish Mitra, Wei-Je Huang, Nirmal R. Saxena, Shu-Yi Yu, Edward J. McCluskey
    Reconfigurable Architecture for Autonomous Self-Repair. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:228-240 [Journal]
  11. T. M. Mak, Angela Krstic, Kwang-Ting (Tim) Cheng, Li-C. Wang
    New Challenges in Delay Testing of Nanometer, Multigigahertz Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:241-247 [Journal]
  12. Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi
    DFT for Delay Fault Testing of High-Performance Digital Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:248-258 [Journal]
  13. Luciano Lavagno
    DAC Highlights. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:259-260 [Journal]

  14. Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:263-0 [Journal]
  15. Hans A. R. Manhaeve
    Current testing for nanotechnologies: Myths, facts, and figures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2004, v:21, n:3, pp:264-0 [Journal]
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