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Journals in DBLP

IEEE Design & Test of Computers
1996, volume: 13, number: 2

  1. Kenneth D. Wagner, Yervant Zorian
    EIC Message. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:2-0 [Journal]
  2. Vishwani D. Agrawal
    1995 Asian Test Symposium carves a niche. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:3-0 [Journal]
  3. Hugo De Man
    Submicron design tools: problems and suppliers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:4- [Journal]
  4. Ajit M. Prabhu, Richard L. Campbell
    Management Perspectives in EDA. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:5-7 [Journal]
  5. Bozena Kaminska, Bernard Courtois
    Guest Editors' Introduction: Mixed Analog and Digital Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:8-9 [Journal]
  6. Thomas Olbrich, Andrew M. D. Richardson
    Design and Self-Test for Switched-Current Building Blocks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:10-17 [Journal]
  7. Ashok Balivada, Jin Chen, Jacob A. Abraham
    Analog Testing with Time Response Parameters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:18-25 [Journal]
  8. Abhijit Chatterjee, Bruce C. Kim, Naveena Nagi
    DC Built-In Self-Test for Linear Analog Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:26-33 [Journal]
  9. Yukiya Miura
    Real-Time Current Testing for A/D Converters. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:34-41 [Journal]
  10. Stephen Dean Brown, Jonathan Rose
    FPGA and CPLD Architectures: A Tutorial. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:42-57 [Journal]
  11. Raul San Martin, John P. Knight
    Optimizing Power in ASIC Behavioral Synthesis. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:58-70 [Journal]
  12. Paul E. Landman, Renu Mehra, Jan M. Rabaey
    An Integrated CAD Environment for Low-Power Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:72-82 [Journal]

  13. A D&T Roundtable Deep-Submicron Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:83-89 [Journal]

  14. Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:93-0 [Journal]

  15. Test Technology Tc Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:94-95 [Journal]
  16. Scott Davidson
    A test puzzle for a TGIF morning. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:2, pp:96-0 [Journal]
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