Journals in DBLP
Rajesh K. Gupta Verification synergies. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:457- [Journal ] Carl Pixley , Sharad Malik Guest Editors' Introduction: Exploring Synergies for Design Verification. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:461-463 [Journal ] Martin Zambaldi , Wolfgang Ecker , Renate Henftling , Matthias Bauer A Layered Adaptive Verification Platform for Simulation, Test, and Emulation. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:464-471 [Journal ] Serdar Tasiran , Yuan Yu , Brannon Batson Linking Simulation with Formal Verification at a Higher Level. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:472-482 [Journal ] Young-Il Kim , Chong-Min Kyung TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:484-493 [Journal ] Jayanta Bhadra , Narayanan Krishnamurthy , Magdy S. Abadir Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:494-502 [Journal ] Shuo Sheng , Michael S. Hsiao Success-Driven Learning in ATPG for Preimage Computation. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:504-512 [Journal ] Ioannis Papaefstathiou Titan II: An IPcomp Processor for 10-Gbps Networks. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:514-523 [Journal ] Frederic Worm , Paolo Ienne , Patrick Thiran , Giovanni De Micheli On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:524-535 [Journal ] Marcel A. Kossel , Martin L. Schmatz Jitter Measurements of High-Speed Serial Links. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:536-543 [Journal ] Glenn H. Chapman , Sunjaya Djaja , Desmond Y. H. Cheung , Yves Audet , Israel Koren , Zahava Koren A Self-Correcting Active Pixel Sensor Using Hardware and Software Correction. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:544-551 [Journal ] Fernanda Lima Kastensmidt , Gustavo Neuberger , Renato Fernandes Hentschke , Luigi Carro , Ricardo Reis Designing Fault-Tolerant Techniques for SRAM-Based FPGAs. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:552-562 [Journal ] Naran Sirisantana , Bipul Chandra Paul , Kaushik Roy Enhancing Yield at the End of the Technology Roadmap. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:563-571 [Journal ] Ikhwan Lee , Yongseok Choi , Youngjin Cho , Yongsoo Joo , Hyeonmin Lim , Hyung Gyu Lee , Hojun Shim , Naehyuck Chang Web-Based Energy Exploration Tool for Embedded Systems. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:572-586 [Journal ] Book Reviews. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:590-591 [Journal ] Victor Berman System-level design language standard needed. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:592-593 [Journal ] Vladimir Hahanov , Raimund Ubar , Subhasish Mitra Conference Reports. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:594-595 [Journal ] DATC Newsletter. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:596- [Journal ] Scott Davidson Design illiteracy. [Citation Graph (0, 0)][DBLP ] IEEE Design & Test of Computers, 2004, v:21, n:6, pp:608- [Journal ]