Journals in DBLP

IEEE Design & Test of Computers
1996, volume: 13, number: 4

1. 
   News. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:3-4 [Journal]
   
2. Bernard Courtois
   Second Therminic Workshop. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:5-0 [Journal]
   
3. Harold S. Stone
   Designing in the multimedia era. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:6-7 [Journal]
   
4. Wojciech Maly
   The future of IC design, testing, and manufacturing. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:8-91 [Journal]
   
5. Stephen Dean Brown
   FPGA Architectural Research: A Survey. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:9-15 [Journal]
   
6. Stephen Dean Brown, Muhammad M. Khellah, Zvonko G. Vranesic
   Minimizing FPGA Interconnect Delays. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:16-23 [Journal]
   
7. Todd A. DeLong, Barry W. Johnson, Joseph A. Profeta III
   A Fault Injection Technique for VHDL Behavioral-Level Models. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:24-33 [Journal]
   
8. Jacob M. Velixon
   Transmission Coefficient Correction for DACs. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:34-39 [Journal]
   
9. Karim Arabi, Bozena Kaminska, Janusz Rzeszut
   BIST for D/A and A/D Converters. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:4, pp:40-49 [Journal]
   
10. Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Circular Self-Test Path for FSMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:50-60 [Journal]
    
11. Jerry M. Soden, Charles F. Hawkins
    IDDQ Testing: Issues Present and Future. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:61-65 [Journal]
    
12. Koji Nakamae, Homare Sakamoto, Hiromu Fujioka
    How ATE Planning Affects LSI Manufacturing Cost. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:66-73 [Journal]
    
13. 
    A D&T Roundtable: Telecommunications System Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:74-81 [Journal]
    
14. 
    IEEE Design & Test of Computers 1996 Annual Index, Volume 13. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:82-85 [Journal]
    
15. 
    Author Guidelines IEEE Design & Test of Computers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:86-87 [Journal]
    
16. 
    Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:93-0 [Journal]
    
17. 
    Test Technology Tc Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:94-95 [Journal]
    
18. Robert C. Aitken
    When tools cry wolf: Testability pitfalls of synthesized designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:4, pp:96-0 [Journal]