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Journals in DBLP

IEEE Design & Test of Computers
2005, volume: 22, number: 5

  1. Rajesh K. Gupta
    On-chip networks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:393- [Journal]
  2. Grant Martin
    Wireless, ESL, DFM, and Power on Stage at 42nd DAC. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:397-398 [Journal]
  3. André Ivanov, Giovanni De Micheli
    Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:399-403 [Journal]
  4. Partha Pratim Pande, Cristian Grecu, André Ivanov, Resve A. Saleh, Giovanni De Micheli
    Design, Synthesis, and Test of Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:404-413 [Journal]
  5. Kees Goossens, John Dielissen, Andrei Radulescu
    Æthereal Network on Chip: Concepts, Architectures, and Implementations. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:414-421 [Journal]
  6. Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo
    Analysis and Implementation of Practical, Cost-Effective Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:422-433 [Journal]
  7. Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli
    Analysis of Error Recovery Schemes for Networks on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:434-442 [Journal]
  8. Christophe Bobda, Ali Ahmadinia
    Dynamic Interconnection of Reconfigurable Modules on Reconfigurable Devices. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:443-451 [Journal]
  9. Javier Resano, Daniel Mozos, Diederik Verkest, Francky Catthoor
    A Reconfiguration Manager for Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:452-460 [Journal]
  10. Braulio Adriano de Mello, Uilian Rafael Feijo Souza, Josue Klafke Sperb, Flávio Rech Wagner
    Tangram: Virtual Integration of IP Components in a Distributed Cosimulation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:462-471 [Journal]

  11. Inventions: A Result of Risk-Taking, Diversity, and Holistic Thinking - An interview with Bernard S. Meyerson, IBM Fellow, Vice President, and Chief Technologist of IBM's System Technology Group. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:472-477 [Journal]
  12. Grant Martin
    Verification by the pound. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:478-479 [Journal]

  13. Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:480-481 [Journal]

  14. Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:482-483 [Journal]
  15. Victor Berman
    An update on IEEE P1647: The e system verification language. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:484-486 [Journal]

  16. DATC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:487- [Journal]
  17. Resve A. Saleh
    An approach that will NoC your SoCs off! [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:5, pp:488- [Journal]
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