Journals in DBLP

IEEE Design & Test of Computers
2003, volume: 20, number: 5

1. Rajesh Gupta
   At-Speed Testing: A Shared Red Brick between Design and Test. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:1-0 [Journal]
   
2. Kenneth M. Butler, Kwang-Ting (Tim) Cheng, Li-C. Wang
   Guest Editors' Introduction: Speed Test and Speed Binning for Complex ICs. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:6-7 [Journal]
   
3. Kee Sup Kim, Subhasish Mitra, Paul G. Ryan
   Delay Defect Characteristics and Testing Strategies. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:8-16 [Journal]
   
4. Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli
   High-Frequency, At-Speed Scan Testing. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:17-25 [Journal]
   
5. Stephen Pateras
   Achieving At-Speed Structural Test. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:26-33 [Journal]
   
6. Alfred L. Crouch, John C. Potter, Jason Doege
   AC Scan Path Selection for Physical Debugging. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:34-40 [Journal]
   
7. Bruce D. Cory, Rohit Kapur, Bill Underwood
   Speed Binning with Path Delay Test in 150-nm Technology. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:41-45 [Journal]
   
8. Robert Madge, Brady Benware, W. Robert Daasch
   Obtaining High Defect Coverage for Frequency-Dependent Defects in Complex ASICs. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:46-53 [Journal]
   
9. Robert C. Aitken, Gordon W. Roberts
   ITC 2003: Breaking Test Interface Bottlenecks. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2003, v:20, n:5, pp:54-0 [Journal]
   
10. Gordon W. Roberts, Robert C. Aitken
    ITC Highlights. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:55-57 [Journal]
    
11. Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian
    Embedded Deterministic Test for Low-Cost Manufacturing. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:58-66 [Journal]
    
12. Darren Anand, Bruce Cowan, Owen Farnsworth, Peter Jakobsen, Steven F. Oakland, Michael Ouellette, Donald L. Wheater
    An On-Chip Self-Repair Calculation and Fusing Methodology. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:67-75 [Journal]
    
13. Bill Eklow, Carl Barnhart, Kenneth P. Parker
    IEEE 1149.6: A Boundary-Scan Standard for Advanced Digital Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:76-83 [Journal]
    
14. Peter C. Maxwell
    Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:84-89 [Journal]
    
15. 
    ARM Twisting with Sir Robin: An Interview with ARM Chairman Sir Robin Saxby. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:90-93 [Journal]
    
16. Jay Lawrence
    Orthogonality of Verilog Data Types and Object Kinds. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:94-96 [Journal]
    
17. 
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:97-99 [Journal]
    
18. 
    DATC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:100-0 [Journal]
    
19. 
    TTTC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:102-103 [Journal]
    
20. Scott Davidson
    All I Know I Learned at ITC. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:5, pp:104-0 [Journal]