Journals in DBLP

IEEE Design & Test of Computers
2002, volume: 19, number: 5

1. Rajesh Gupta
   Sustaining an Industry Obsession. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:1-0 [Journal]
   
2. Jaume Segura, Peter C. Maxwell
   Guest Editors' Introduction: Defect-Oriented Testing in the Deep-Submicron Era. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:5-7 [Journal]
   
3. Sagar S. Sabade, D. M. H. Walker
   IDDQ Test: Will It Survive the DSM Challenge? [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:8-16 [Journal]
   
4. Rosa Rodríguez-Montañés, Paul Volf, José Pineda de Gyvez
   Resistance Characterization for Weak Open Defects. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:18-26 [Journal]
   
5. Xavier Aragonès, José Luis González, Francesc Moll, Antonio Rubio
   Noise Generation and Coupling Mechanisms in Deep-Submicron ICs. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:27-35 [Journal]
   
6. Ali Keshavarzi, James Tschanz, Siva Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins
   Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:36-43 [Journal]
   
7. Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel, Hans-Joachim Wunderlich
   High Defect Coverage with Low-Power Test Sequences in a BIST Environment. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:44-52 [Journal]
   
8. Robert C. Aitken, Donald L. Wheater
   Guest Editors' Introduction: Stressing the Fundamentals. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:54-55 [Journal]
   
9. Shuo Sheng, Michael S. Hsiao
   Efficient Sequential Test Generation Based on Logic Simulation. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 2002, v:19, n:5, pp:56-64 [Journal]
   
10. Carl Barnhart, Vanessa Brunkhorst, Frank Distler, Owen Farnsworth, Andrew Ferko, Brion L. Keller, David Scott, Bernd Könemann, Takeshi Onodera
    Extending OPMISR beyond 10x Scan Test Efficiency. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:65-72 [Journal]
    
11. W. Robert Daasch, James McNames, Robert Madge, Kevin Cota
    Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:74-81 [Journal]
    
12. Sule Ozev, Christian Olgaard, Alex Orailoglu
    Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:82-91 [Journal]
    
13. Marcello Dalpasso, Alessandro Bogliolo, Luca Benini
    Virtual Simulation of Distributed IP-Based Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:92-104 [Journal]
    
14. 
    Formal Verification: Current Use and Future Perspectives. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:105-113 [Journal]
    
15. 
    Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:114-115 [Journal]
    
16. 
    Test Technology TC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:116-117 [Journal]
    
17. 
    Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:118-0 [Journal]
    
18. Krishnendu Chakrabarty, Erik Jan Marinissen
    How Useful are the ITC 02 SoC Test Benchmarks? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2002, v:19, n:5, pp:120- [Journal]