Journals in DBLP

IEEE Design & Test of Computers
1998, volume: 15, number: 1

1. Yervant Zorian
   D&T: 15th Year in Service. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:1-0 [Journal]
   
2. 
   News. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:4-5 [Journal]
   
3. Teruhiko Yamada
   1997 Asian Test Symposium. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:6-0 [Journal]
   
4. Dilip K. Bhavsar, Yervant Zorian
   ITC 97 Panel Sessions. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:7- [Journal]
   
5. Fabrizio Lombardi
   Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:8-9 [Journal]
   
6. Vaughn Betz, Jonathan Rose
   How Much Logic Should Go in an FPGA Logic Block? [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:10-15 [Journal]
   
7. Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky
   Rothko: A Three-Dimensional FPGA. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:16-23 [Journal]
   
8. Shanzhen Xing, William W. H. Yu
   FPGA Adders: Performance Evaluation and Optimal Design. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:24-29 [Journal]
   
9. Roger Woods, David W. Trainor, Jean-Paul Heron
   Applying an XC6200 to Real-Time Image Processing. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1998, v:15, n:1, pp:30-38 [Journal]
   
10. Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara
    Universal Fault Diagnosis for Lookup Table FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:39-44 [Journal]
    
11. Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian
    Testing the Interconnect of RAM-Based FPGAs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:45-50 [Journal]
    
12. Kenneth L. Shepard, Vinod Narayanan
    Conquering Noise in Deep-Submicron Digital ICs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:51-62 [Journal]
    
13. Stefano Barbagallo, Davide Medina, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda
    Integrating Online and Offline Testing of a Switching Memory. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:63-70 [Journal]
    
14. Felice Balarin, Luciano Lavagno, Praveen K. Murthy, Alberto L. Sangiovanni-Vincentelli
    Scheduling for Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:71-82 [Journal]
    
15. 
    A D&T Roundtable: Relative Effectiveness of Tests. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:83-90 [Journal]
    
16. 
    Test Technology TC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:92-94 [Journal]
    
17. 
    Design Automation TC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:95-0 [Journal]
    
18. Hideo Fujiwara
    Needed: Third-generation ATPG Benchmarks. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1998, v:15, n:1, pp:96-0 [Journal]