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Journals in DBLP

IEEE Design & Test of Computers
1997, volume: 14, number: 1


  1. Keeping in touch: Reader survey results; planned e-mail survey. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:4-5 [Journal]
  2. J. Wilson
    CFI leads development of design data standard. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:6- [Journal]

  3. News. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:7- [Journal]
  4. Marc E. Levitt
    Guest Editor's Introduction: Microprocessors Lead the Way in Complex Design. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:8-9 [Journal]
  5. Marc E. Levitt
    Designing UltraSparc for Testability. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:10-17 [Journal]
  6. Lynn Youngs, Siva Paramanandam
    Mapping and Repairing Embedded-Memory Defects. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:18-24 [Journal]
  7. Dilip K. Bhavsar, John H. Edmondson
    Alpha 21164 Testability Strategy. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:25-33 [Journal]
  8. Jainendra Kumar
    Prototyping the M68060 for Concurrent Verification. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:34-41 [Journal]
  9. Margarida F. Jacome, Viktor S. Lapinskii
    NREC: Risk Assessment and Planning of Complex Designs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:42-49 [Journal]
  10. Robert Wu, Jerry Gerner, Richard Wheelus, Kevin Lew
    Testing Logic-Intensive Memory ICs on Memory Testers. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:50-54 [Journal]
  11. Al Bailey, Tim Lada, Jim Preston
    Collateral ASIC Test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:55-63 [Journal]
  12. Ghassan Al Hayek, Yves Le Traon, Chantal Robach
    Impact of System Partitioning on Test Cost. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:64-74 [Journal]

  13. Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:75-83 [Journal]

  14. Panel Summaries. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:84-87 [Journal]

  15. Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:88-90 [Journal]

  16. Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:92-93 [Journal]

  17. Test Technology Tc Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:94-95 [Journal]
  18. Scott Davidson
    George learns test. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1997, v:14, n:1, pp:96-0 [Journal]
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