The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Design & Test of Computers
2003, volume: 20, number: 1

  1. Rajesh Gupta
    From the Editor in Chief: Twenty years! [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:1-0 [Journal]
  2. Alex Orailoglu, Alexander V. Veidenbaum
    Guest Editors' Introduction: Application-Specific Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:6-7 [Journal]
  3. Wolfgang Raab, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Ulrich Ramacher, Christian Sauer, Axel Techmer
    A 100-GOPS Programmable Processor for Vehicle Vision Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:8-16 [Journal]
  4. Peter Petrov, Alex Orailoglu
    Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:18-25 [Journal]
  5. Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt
    Compilation Approach for Coarse-Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:26-33 [Journal]
  6. Oliver Wahlen, Manuel Hohenauer, Rainer Leupers, Heinrich Meyr
    Instruction Scheduler Generation for Retargetable Compilation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:34-41 [Journal]
  7. Jörg E. Vollrath
    Testing and Characterization of SDRAMs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:42-50 [Journal]
  8. Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski
    2D Test Sequence Generators. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:51-59 [Journal]
  9. Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei
    An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:60-67 [Journal]
  10. Jean Michel Daga, Caroline Papaix, Marc Merandat, Stephane Ricard, Giuseppe Medulla, Jeanine Guichaoua, Daniel Auvergne
    Design Techniques for EEPROMs Embedded in Portable Systems on Chips. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:68-75 [Journal]
  11. Luigi Carro, Marcelo Negreiros, Gabriel Parmegiani Jahn, Adão Antônio de Souza Jr., Denis Teixeira Franco
    Circuit-Level Considerations for Mixed-Signal Programmable Components. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:76-84 [Journal]
  12. Andrew B. Kahng
    Error Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:86-87 [Journal]
  13. Carol Stolicny
    ITC 2002 Panels. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:88-90 [Journal]
  14. Peter J. Ashenden
    Boundary Scan Test Standards. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:91-92 [Journal]
  15. Ahmed Amine Jerraya
    Hot Topics at HLDVT 02. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:92-0 [Journal]

  16. DATC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:93-0 [Journal]

  17. TTTC Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:94-95 [Journal]
  18. Frank Vahid
    Making the Best of Those Extra Transistors. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2003, v:20, n:1, pp:96-0 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002