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Journals in DBLP

IEEE Design & Test of Computers
2005, volume: 22, number: 4

  1. Rajesh K. Gupta
    Nanotechnology: Where science of the small meets math of the large. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:289- [Journal]
  2. Giovanni De Micheli, Al Dunlop
    IEEE Council for Electronic Design Automation: A new beginning. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:293-294 [Journal]
  3. R. Iris Bahar, Mehdi Baradaran Tahoori, Sandeep K. Shukla, Fabrizio Lombardi
    Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:295-297 [Journal]
  4. Darshan D. Thaker, Francois Impens, Isaac L. Chuang, Rajeevan Amirtharajah, Frederic T. Chong
    Recursive TMR: Scaling Fault Tolerance in the Nanoscale Era. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:298-305 [Journal]
  5. André DeHon, Helia Naeimi
    Seven Strategies for Tolerating Highly Defective Fabrication. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:306-315 [Journal]
  6. Chen He, Margarida F. Jacome, Gustavo de Veciana
    A Reconfiguration-Based Defect-Tolerant Design Paradigm for Nanotechnologies. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:316-326 [Journal]
  7. Jie Han, Jianbo Gao, Yan Qi 0003, Pieter Jonker, José A. B. Fortes
    Toward Hardware-Redundant, Fault-Tolerant Logic for Nanoelectronics. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:328-339 [Journal]
  8. Daniele Rossi, André K. Nieuwland, Atul Katoch, Cecilia Metra
    New ECC for Crosstalk Impact Minimization. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:340-348 [Journal]
  9. Mark L. Chang, Scott Hauck
    Précis: A Usercentric Word-Length Optimization Tool. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:349-361 [Journal]
  10. Chong Zhao, Sujit Dey, Xiaoliang Bai
    Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:362-375 [Journal]
  11. Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan
    Modeling and Analysis of Parametric Yield under Power and Performance Constraints. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:376-385 [Journal]
  12. Scott Davidson
    BIST the hard way. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:386-387 [Journal]
  13. Luigi Carro
    Adding value to design and test through education: What are the challenges? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:388- [Journal]

  14. Conference Reports. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:389-390 [Journal]

  15. Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:391- [Journal]
  16. Scott Davidson
    What's the problem? [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 2005, v:22, n:4, pp:392- [Journal]
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