Journals in DBLP

IEEE Design & Test of Computers
1996, volume: 13, number: 3

1. 
   News. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:4- [Journal]
   
2. Yervant Zorian, Tom Anderson, Yvon Savaria, Claude Thibeault, André Ivanov
   Panel Summaries. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:6-112 [Journal]
   
3. Gil Philips, Yervant Zorian, Charles W. Rosenthal, Bozena Kaminska
   Conference Reports. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:8-144 [Journal]
   
4. Vijay K. Madisetti, Mark A. Richards
   Guest Editors' Introduction: Advances in Rapid Prototyping of Digital Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:9-11 [Journal]
   
5. Vijay K. Madisetti
   Rapid Digital System Prototyping: Current Practice, Future Challenges. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:12-22 [Journal]
   
6. James H. M. Malley
   RASSP: Changing the Paradigm of Electronic-System Design. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:23-31 [Journal]
   
7. Richard M. Sedmak, John S. Evans
   Spanning the Product Life Cycle: RASSP DFT. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:32-42 [Journal]
   
8. Carolyn Kuttner
   Hardware-Software Codesign Using Processor Synthesis. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:43-53 [Journal]
   
9. Lan-Rong Dung, Vijay K. Madisetti
   Conceptual Prototyping of Scalable Embedded DSP Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Design & Test of Computers, 1996, v:13, n:3, pp:54-65 [Journal]
   
10. Sandi Habinc, Peter Sinander
    Using VHDL for Board Level Simulation. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:66-78 [Journal]
    
11. Harald P. E. Vranken, Marc F. Witteman, Ronald C. van Wuijtswinkel
    Design for Testability in Hardware-Software Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:79-87 [Journal]
    
12. Ramesh Karri, Karin Högstedt, Alex Orailoglu
    Computer-Aided Design of Fault-Tolerant VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:88-96 [Journal]
    
13. Adam Cron
    A D&T Special Report: P1149.4 Mixed-Signal Test Bus. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:98-101 [Journal]
    
14. 
    A D&T Roundtable: Deep-Submicron Test in cooperation with the Test Technology Technical Committee. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:102-108 [Journal]
    
15. 
    Design Automation Technical Committee Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:116-117 [Journal]
    
16. 
    Test Technology Tc Newsletter. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:118-119 [Journal]
    
17. Scott Davidson
    How to achieve 95% fault coverage without really trying. [Citation Graph (0, 0)][DBLP]
    IEEE Design & Test of Computers, 1996, v:13, n:3, pp:120-0 [Journal]