Journals in DBLP
Eugene Asarin , Oded Maler , Sergio Yovine Preface. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Arnaldo V. Moura , Guilherme A. Pinto Classes of Timed Automata and the Undecidability of Universality. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] M. Oliver Möller , Harald Rueß , Maria Sorea Predicate Abstraction for Dense Real-Time System. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] M. Oliver Möller Parking can get you there faster - Model Augmentation to Speed up Real-Time Model-Checking. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Eric Mercer , Chris J. Myers , Tomohiro Yoneda Modular Synthesis of Timed Circuits using Partial Order Reduction. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Philipp Lucas Timed Semantics of Message Sequence Charts Based on Timed Automata. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Pao-Ann Hsiung , Chuen-Hau Gao Formal Synthesis of Real-Time Embedded Software by Time-Memory Scheduling of Colored Time Petri Nets. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Martijn Hendriks , Kim Guldstrand Larsen Exact Acceleration of Real-Time Model Checking. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Dimitar P. Guelev , Dang Van Hung Prefix and Projection onto State in Duration Calculus. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Nawel Gharbi , Malika Ioualalen Performance Analysis of Retrial Queueing Systems Using Generalized Stochastic Petri Nets. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Jérôme Ermont , Frédéric Boniol TPAP: an Algebra of Preemptive Processes for Verifying Real-Time Systems with Shared Resources. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Giorgio C. Buttazzo , Avi Efrati , John N. Hooker , Claude Le Pape , Joseph Sifakis Abstracts of Invited Talks. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Víctor A. Braberman , Carlos López Pombo , Alfredo Olivero On Improving Backwards Verification of Timed Automata. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Marius Bozga , Hou Jianmin , Oded Maler , Sergio Yovine Verification of Asynchronous Circuits using Timed Automata. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Marc Boyer Translation from timed Petri nets with intervals on transitions to intervals on places (with urgency) [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Hanifa Boucheneb , Gérard Berthelot Contraction of the ITCPN State Space. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ] Paritosh K. Pandya Interval Duration Logic: Expressiveness and Decidability. [Citation Graph (0, 0)][DBLP ] Electr. Notes Theor. Comput. Sci., 2002, v:65, n:6, pp:- [Journal ]