Journals in DBLP
Ganesh Gopalakrishnan , Warren A. Hunt Jr. Industrial Practice of Formal Hardware Verification: A Sampling. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:95-99 [Journal ] Shoham Ben-David , Cindy Eisner , Daniel Geist , Yaron Wolfsthal Model Checking at IBM. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:101-108 [Journal ] Mani Azimi , Ching-Tsun Chou , Akhilesh Kumar , Victor W. Lee , Phanindra K. Mannava , Seungjoon Park Experience with Applying Formal Methods to Protocol Specification and System Architecture. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:109-116 [Journal ] Magdy S. Abadir , Ken Albin , John Havlicek , Narayanan Krishnamurthy , Andrew K. Martin Formal Verification Successes at Motorola. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:117-123 [Journal ] Rajeev Joshi , Leslie Lamport , John Matthews , Serdar Tasiran , Mark R. Tuttle , Yuan Yu Checking Cache-Coherence Protocols with TLA+ . [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:125-131 [Journal ] Steven M. German Formal Design of Cache Memory Protocols in IBM. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:133-141 [Journal ] John Harrison Formal Verification of Square Root Algorithms. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:143-153 [Journal ] Pascalin Amagbégnon , Uri Barkai Verifying the Implementation of an Error Control Code. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:155-161 [Journal ] William Adams , Warren A. Hunt Jr. , Damir Jamsek Verisym: Verifying Circuits by Symbolic Simulation. [Citation Graph (0, 0)][DBLP ] Formal Methods in System Design, 2003, v:22, n:2, pp:163-173 [Journal ]