Journals in DBLP

IBM Journal of Research and Development
2002, volume: 46, number: 2-3

1. G. G. Shahidi
   SOI technology for the GHz era. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:121-132 [Journal]
   
2. H.-S. Philip Wong
   Beyond the conventional transistor. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:133-168 [Journal]
   
3. Edward J. Nowak
   Maintaining the benefits of CMOS scaling when scaling bogs down. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:169-186 [Journal]
   
4. Jack A. Mandelman, Robert H. Dennard, Gary B. Bronner, John K. DeBrosse, Rama Divakaruni, Yujun Li, Carl J. Raden
   Challenges and future directions for the scaling of dynamic random-access memory (DRAM). [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:187-222 [Journal]
   
5. Ravi Nair
   Effect of increasing chip density on the evolution of computer architectures. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:223-234 [Journal]
   
6. David J. Frank
   Power-constrained CMOS scaling limits. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:235-344 [Journal]
   
7. James D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl
   Interconnect opportunities for gigascale integration. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:245-264 [Journal]
   
8. James H. Stathis
   Reliability limits for the gate insulator in CMOS technology. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:265-286 [Journal]
   
9. Ernest Y. Wu, Edward J. Nowak, Alex Vayshenker, Wing L. Lai, David L. Harmon
   CMOS scaling beyond the 100-nm node with silicon-dioxide-based gate dielectrics. [Citation Graph (0, 0)][DBLP]
   IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:287-298 [Journal]
   
10. Carlton M. Osburn, Indong Kim, Sungkee Han, Indranil De, Kam F. Yee, Shyam Gannavaram, SungJoo Lee, Chung-Ho Lee, Zhijiong J. Luo, Wenjuan Zhu, John R. Hauser, Dim-Lee Kwong, Gerald Lucovsky, T. P. Ma, Mehmet C. Öztürk
    Vertically scaled MOSFET gate stacks and junctions: How far are we likely to go? [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:299-316 [Journal]
    
11. Paul D. Agnello
    Process requirements for continued scaling of CMOS-the need and prospects for atomic-level manipulation. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:317-338 [Journal]
    
12. Mark E. Law
    Process modeling for future technologies. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:339-346 [Journal]
    
13. Anthony Lochtefeld, Ihsan J. Djomehri, Ganesh Samudra, Dimitri A. Antoniadis
    New insights into carrier transport in n-MOSFETs. [Citation Graph (0, 0)][DBLP]
    IBM Journal of Research and Development, 2002, v:46, n:2-3, pp:347-358 [Journal]