Journals in DBLP

Int. J. Neural Syst.
2000, volume: 10, number: 3

1. Davide Anguita, Andrea Boni, Sandro Ridella
   Digital VLSI Algorithms and Architectures for Support Vector Machines. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:159-170 [Journal]
   
2. Joakim Waldemark, Mikael Millberg, Thomas Lindblad, Karina Waldemark, Vlatko Becanovic
   Implementation Of A Pulse Coupled Neural Network in FPGA. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:171-177 [Journal]
   
3. Teresa Serrano-Gotarredona, Andreas G. Andreou, Bernabé Linares-Barranco
   A Programmable VLSI Filter Architecture for Application in Real-Time Vision Processing Systems. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:179-190 [Journal]
   
4. Bogdan M. Wilamowski, J. Binfet, M. O. Kaynak
   VLSI Implementation of Neural Networks. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:191-197 [Journal]
   
5. Tuan A. Duongmm, Allen R. Stubberud
   Convergence Analysis of Cascade Error Projection - An Efficient Learning Algorithm for Hardware Implementation. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:199-210 [Journal]
   
6. Leonardo Maria Reyneri, Marcello Chiaberge, Luciano Lavagno, Begoña Pino, E. Miranda
   Simulink-Based HW/SW Codesign of Embedded Neuro-Fuzzy Systems. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:211-226 [Journal]
   
7. Omer F. Rana
   Automating Parallel Implementation of Neural Learning Algorithms. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:227-241 [Journal]
   
8. Bernard Girau
   FPNA: Interaction Between FPGA and Neural Computation. [Citation Graph (0, 0)][DBLP]
   Int. J. Neural Syst., 2000, v:10, n:3, pp:243-259 [Journal]