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Journals in DBLP

IJPRAI
1995, volume: 9, number: 2

  1. Martin C. Herbordt, Charles C. Weems
    Enpassant: An Environment for Evaluating Massively Parallel Array Architectures for Spatially Mapped Applications. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:175-200 [Journal]
  2. Suchendra M. Bhandarkar, Hamid R. Arabnia, Jeffrey W. Smith
    A Reconfigurable Architecture for Image Processing and Computer Vision. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:201-229 [Journal]
  3. N. Venkateswaran, S. Pattabiraman, R. Devanathan, B. Kumaran, Ashraf Ahmed, Sankara Narayanan, Radharamanan
    A Design Methodology for Very Large Array Processors - Part 1: Gipop Processor Array. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:231-262 [Journal]
  4. N. Venkateswaran, S. Pattabiraman, J. DeSouza, G. Sriram, R. Srinivasan, R. Sankar, G. Suresh
    A Design Methodology for Very Large Array Processors - Part 2: Pacube VLSI Arrays. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:263-301 [Journal]
  5. Arup K. Bhattacharya, Syed S. Haider
    A VLSI Implementation of the Inverse Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:303-314 [Journal]
  6. Maria Grazia Albanesi, Marco Ferretti
    Systolic Merging and Ranking of Votes for the Generalized Hough Transform. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:315-341 [Journal]
  7. Tinku Acharya, Amar Mukherjee
    High-Speed Parallel VLSI Architectures for Image Decorrelation. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:343-365 [Journal]
  8. Raghu Sastry, N. Ranganathan
    PMAC: A Polygon Matching Chip. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:367-385 [Journal]
  9. Houcine Senoussi, Ahmed Saoudi
    Quadtree Algorithms for Template Matching on Mesh Connected Computer. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:387-410 [Journal]
  10. Kuo-Liang Chung
    A Fast Pattern-Matching Algorithm on Modular Mesh-Connected Computers with Multiple Buses. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:411-419 [Journal]
  11. Vincenzo Catania, Giuseppe Ascia
    A VLSI Parallel Architecture for Fuzzy Expert Systems. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:421-447 [Journal]
  12. Indradeep Ghosh, Bandana Majumdar
    VLSI Implementation of An Efficient ASIC Architecture for Real-Time Rotation of Digital Images. [Citation Graph (0, 0)][DBLP]
    IJPRAI, 1995, v:9, n:2, pp:449-462 [Journal]
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