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Journals in DBLP
Integration
2006, volume: 39, number: 3
- Jihyun Lee, Yong-Bin Kim
ASLIC: A low power CMOS analog circuit design automation. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:157-181 [Journal]
- Victor R. L. Shen
A PN-based approach to the high-level synthesis of digital systems. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:182-204 [Journal]
- J. Tong, X. Zou, X. B. Shen
Simulation for a novel vertical SOI configuration. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:205-210 [Journal]
- Mohamed Raseen, P. W. Chandana Prasad, Ali Assi
An efficient estimation of the ROBDD's complexity. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:211-228 [Journal]
- Nabil Abu-Khader, Pepe Siy
Systolic Galois field exponentiation in a multiple-valued logic technique. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:229-251 [Journal]
- Rezaul Haque, Andrzej Sendrowski, Bob Baltar, Saad Monasa
Design of a high-speed, low-noise CMOS data output buffer. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:252-266 [Journal]
- Nagu R. Dhanwada, Alex Doboli, Adrián Núñez-Aldana, Ranga Vemuri
Hierarchical constraint transformation based on genetic optimization for analog system synthesis. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:267-290 [Journal]
- Joanna C. K. Lai, Waleed H. Abdulla, Stephan Hussmann
Hardware implementation of a sub-pixel algorithm for real-time saw blade deflection monitoring. [Citation Graph (0, 0)][DBLP]
Integration, 2006, v:39, n:3, pp:291-309 [Journal]
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