Journals in DBLP
Integration Lei Yang , C.-J. Richard Shi FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits. [Citation Graph (0, 0)][DBLP ] Journal ] Saurabh N. Adya , Igor L. Markov , Paul G. Villarrubia On whitespace and stability in physical synthesis. [Citation Graph (0, 0)][DBLP ] Journal ] Saeed Safari , Amir-Hossein Jahangir , Hadi Esmaeilzadeh A parameterized graph-based framework for high-level test synthesis. [Citation Graph (0, 0)][DBLP ] Journal ] Donald Shaw , Dhamin Al-Khalili , Come Rozon Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries. [Citation Graph (0, 0)][DBLP ] Journal ] Anu Gupta , Bipin Kulkarni Automation of clock distribution network design for digital integrated circuits using divide and conquer technique. [Citation Graph (0, 0)][DBLP ] Journal ] Tsung-Yi Ho , Yao-Wen Chang , Sao-Jie Chen Multilevel routing with jumper insertion for antenna avoidance. [Citation Graph (0, 0)][DBLP ] Journal ] S. Engels , Robin Wilson , Nadine Azémard , Philippe Maurine A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects. [Citation Graph (0, 0)][DBLP ] Journal ] Jingyu Xu , Xianlong Hong , Tong Jing , Ling Zhang , Jun Gu A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design. [Citation Graph (0, 0)][DBLP ] Journal ] Zhiyuan Yan , Dilip V. Sarwate , Zhongzhi Liu Erratum to: "High-speed systolic architectures for finite field inversion" [Integration 38(3) (2005) 383-398]. [Citation Graph (0, 0)][DBLP ] Journal ] 