Journals in DBLP

Integration
2005, volume: 38, number: 3

1. Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell
   An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:341-352 [Journal]
   
2. Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
   Quality-of-service and error control techniques for mesh-based network-on-chip architectures. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:353-382 [Journal]
   
3. Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu
   High-speed systolic architectures for finite field inversion. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:383-398 [Journal]
   
4. Roghoyeh Salmeh, Brent Maundy
   Complete automatic Q tuning system on a chip. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:399-415 [Journal]
   
5. Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
   Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:417-437 [Journal]
   
6. Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
   Equidistance routing in high-speed VLSI layout design. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:439-449 [Journal]
   
7. Shalini Ghosh, F. Joel Ferguson
   Detection probabilities of interconnect breaks: an analysis. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:451-465 [Journal]
   
8. Franco Fummi, Cristina Marconcini, Graziano Pravadelli
   Logic-level mapping of high-level faults. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:467-490 [Journal]
   
9. Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
   Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies. [Citation Graph (0, 0)][DBLP]
   Integration, 2005, v:38, n:3, pp:491-504 [Journal]
   
10. Davood Shahrjerdi, Bahman Hekmatshoar, Ali Khaki-Firooz, Ali Afzali-Kusha
    Optimization of the V_T control method for low-power ultra-thin double-gate SOI logic circuits. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:505-513 [Journal]
    
11. Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
    Low-power branch prediction techniques for VLIW architectures: a compiler-hints based approach. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:515-524 [Journal]
    
12. Jong-Ru Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:525-540 [Journal]
    
13. Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier
    Automatic cell placement for quantum-dot cellular automata. [Citation Graph (0, 0)][DBLP]
    Integration, 2005, v:38, n:3, pp:541-548 [Journal]