
Journals in DBLP
Integration 2005, volume: 38, number: 3
 Sankar Barua, Joan Carletta, Kishore A. Kotteri, Amy E. Bell
An efficient architecture for liftingbased twodimensional discrete wavelet transforms. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:341352 [Journal]
 Praveen Vellanki, Nilanjan Banerjee, Karam S. Chatha
Qualityofservice and error control techniques for meshbased networkonchip architectures. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:353382 [Journal]
 Zhiyuan Yan, Dilip V. Sarwate, Zhongzhi Liu
Highspeed systolic architectures for finite field inversion. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:383398 [Journal]
 Roghoyeh Salmeh, Brent Maundy
Complete automatic Q tuning system on a chip. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:399415 [Journal]
 Hassan Hassan, Mohab Anis, Mohamed I. Elmasry
Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:417437 [Journal]
 Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi
Equidistance routing in highspeed VLSI layout design. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:439449 [Journal]
 Shalini Ghosh, F. Joel Ferguson
Detection probabilities of interconnect breaks: an analysis. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:451465 [Journal]
 Franco Fummi, Cristina Marconcini, Graziano Pravadelli
Logiclevel mapping of highlevel faults. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:467490 [Journal]
 Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky
Characterization of logic circuit techniques and optimization for highleakage CMOS technologies. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:491504 [Journal]
 Davood Shahrjerdi, Bahman Hekmatshoar, Ali KhakiFirooz, Ali AfzaliKusha
Optimization of the V_{T} control method for lowpower ultrathin doublegate SOI logic circuits. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:505513 [Journal]
 Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon
Lowpower branch prediction techniques for VLIW architectures: a compilerhints based approach. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:515524 [Journal]
 JongRu Guo, Chao You, Kuan Zhou, Michael Chu, Peter F. Curran, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald
A 10 GHz 4: 1 MUX and 1: 4 DEMUX implemented by a Gigahertz SiGe FPGA for fast ADC. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:525540 [Journal]
 Ramprasad Ravichandran, Sung Kyu Lim, Michael T. Niemier
Automatic cell placement for quantumdot cellular automata. [Citation Graph (0, 0)][DBLP] Integration, 2005, v:38, n:3, pp:541548 [Journal]
