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Journals in DBLP
Integration 1998, volume: 26, number: 1-2
- Bernd Becker
Testing with decision diagrams. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:5-20 [Journal]
- Irith Pomeranz, Sudhakar M. Reddy
Delay fault models for VLSI circuits1. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:21-40 [Journal]
- Yong Chang Kim, Kewal K. Saluja
Sequential test generators: past, present and future. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:41-54 [Journal]
- Hans-Joachim Wunderlich
BIST for systems-on-a-chip. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:55-78 [Journal]
- Indradeep Ghosh, Niraj K. Jha
High-level test synthesis: a survey. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:79-99 [Journal]
- Michiko Inoue, Hideo Fujiwara
An approach to test synthesis from higher level. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:101-116 [Journal]
- Anurag Gupta, Kanad Chakraborty, Pinaki Mazumder
FTROM: A Silicon Compiler for Fault-tolerant ROMs. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:117-140 [Journal]
- Vishwani D. Agrawal
Design of mixed-signal systems for testability. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:141-150 [Journal]
- Mani Soma
Mixed-signal on-chip timing measurements. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:151-165 [Journal]
- Antoni Ferré, Eugeni Isern, Josep Rius, Rosa Rodríguez-Montañés, Joan Figueras
IDDQ testing: state of the art and future trends. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:167-196 [Journal]
- Michael Nicolaidis
On-line testing for VLSI: state of the art and trends. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:197-209 [Journal]
- Masahide Nakamura, Tohru Kikuno
A new approach in feature interaction testing. [Citation Graph (0, 0)][DBLP] Integration, 1998, v:26, n:1-2, pp:211-223 [Journal]
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