Journals in DBLP

Integration
2006, volume: 39, number: 2

1. Kaushik Roy
   Guest Editorial. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:2, pp:63- [Journal]
   
2. Bipul Chandra Paul, Amit Agarwal, Kaushik Roy
   Low-power design techniques for scaled technologies. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:2, pp:64-89 [Journal]
   
3. Jia Di, Jiann S. Yuan, Ronald F. DeMara
   Improving power-awareness of pipelined array multipliers using two-dimensional pipeline gating and its application on FIR design. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:2, pp:90-112 [Journal]
   
4. David Atienza, Stylianos Mamagkakis, Francesco Poletti, Jose Manuel Mendias, Francky Catthoor, Luca Benini, Dimitrios Soudris
   Efficient system-level prototyping of power-aware dynamic memory managers for embedded systems. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:2, pp:113-130 [Journal]
   
5. Matthias Müller, Sven Simon, Holger Gryska, Andreas Wortmann, Steffen Buch
   Low power synthesizable register files for processor and IP cores. [Citation Graph (0, 0)][DBLP]
   Integration, 2006, v:39, n:2, pp:131-155 [Journal]