Journals in DBLP

Integration
2001, volume: 30, number: 2

1. Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson
   Delay-insensitive gate-level pipelining. [Citation Graph (0, 0)][DBLP]
   Integration, 2001, v:30, n:2, pp:103-131 [Journal]
   
2. Hasan Ymeri, Bart Nauwelaers, Karen Maex
   Frequency-dependent mutual resistance and inductance formulas for coupled IC interconnects on an Si-SiO2 substrate. [Citation Graph (0, 0)][DBLP]
   Integration, 2001, v:30, n:2, pp:133-141 [Journal]
   
3. Xiaoping Tang, D. F. Wong
   Network flow based buffer planning. [Citation Graph (0, 0)][DBLP]
   Integration, 2001, v:30, n:2, pp:143-155 [Journal]
   
4. Soumen Maity, Bimal K. Roy, Amiya Nayak
   Enumerating catastrophic fault patterns in VLSI arrays with both uni- and bidirectional links. [Citation Graph (0, 0)][DBLP]
   Integration, 2001, v:30, n:2, pp:157-168 [Journal]
   
5. Kiamal Z. Pekmestzi, Nikos K. Moshopoulos
   A bit-interleaved systolic architecture for a high-speed RSA system. [Citation Graph (0, 0)][DBLP]
   Integration, 2001, v:30, n:2, pp:169-175 [Journal]