
Journals in DBLP
Integration 2007, volume: 40, number: 1
 Nadia Nedjah, Luiza de Macedo Mourelle
Embedded cryptographic hardware. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:12 [Journal]
 Akashi Satoh, Tadanobu Inoue
ASIChardwarefocused comparison for hash functions MD5, RIPEMD160, and SHS. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:310 [Journal]
 T. S. Ganesh, Michael T. Frederick, T. S. B. Sudarshan, Arun K. Somani
Hashchip: A sharedresource multihash function processor architecture on FPGA. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:1119 [Journal]
 FrançoisXavier Standaert, Gilles Piret, Gaël Rouvroy, JeanJacques Quisquater
FPGA implementations of the ICEBERG block cipher. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:2027 [Journal]
 Tim Kerins, William P. Marnane, Emanuel M. Popovici
Versatile hardware architectures for GF(p^{m}) arithmetic in public key cryptography. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:2835 [Journal]
 Nadia Nedjah, Luiza de Macedo Mourelle
Efficient and secure cryptographic systems based on addition chains: Hardware design vs. software/hardware codesign. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:3644 [Journal]
 Alireza Hodjat, Lejla Batina, David Hwang, Ingrid Verbauwhede
HW/SW codesign of a hyperelliptic curve cryptosystem using a microcode instruction set coprocessor. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:4551 [Journal]
 Eric Peeters, FrançoisXavier Standaert, JeanJacques Quisquater
Power and electromagnetic analysis: Improved model, consequences and comparisons. [Citation Graph (0, 0)][DBLP] Integration, 2007, v:40, n:1, pp:5260 [Journal]
