Journals in DBLP

Journal of Circuits, Systems, and Computers
2005, volume: 14, number: 4

1. Sukanya Parui, Soumitro Banerjee, S. Sengupta, B. Basak
   Experimental Verification of Border Collision Bifurcation Due to Mode Transition in a Current Mode Controlled Buck Converter. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:653-666 [Journal]
   
2. Soliman A. Mahmoud
   Digitally Controlled Cmos Balanced Output Transconductor and Application to Variable Gain Amplifier and Gm-c Filter on Field Programmable Analog Array. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:667-684 [Journal]
   
3. Hsiao Wei Su, Yichuang Sun
   Performance Analysis and Comparison of Multiple Loop Feedback Ota-c Filters. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:685-720 [Journal]
   
4. Cheng Fu, Bogdan J. Falkowski
   Ternary Fixed Polarity Linear Kronecker Transforms and their Comparison with Ternary Reed-muller Transform. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:721-734 [Journal]
   
5. Ashok Kumar, Magdy A. Bayoumi
   A Fast Scheduling Algorithm for Low Power Design. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:735-756 [Journal]
   
6. Cristina Morel, Marc Bourcerie, François Chapeau-Blondeau
   Improvement of Power Supply Electromagnetic Compatibility by Extension of Chaos Anticontrol. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:757-770 [Journal]
   
7. B. Dam, K. Banerjee, K. Majumdar, R. Banerjee, D. Patranabis
   A Zero Phase-lag Homodyne Demodulation Technique for Synchronous Measurement Applications and its Fpga Implementation. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:771-792 [Journal]
   
8. Li Jiao, Hejiao Huang, To-Yat Cheung
   Property-preserving Composition by Place Merging. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:793-812 [Journal]
   
9. Jiang-bo Qian, Hong-bing Xu, Yisheng Dong, Xue-jun Liu, Yong-li Wang
   FPGA Acceleration Window Joins over Multiple Data Streams. [Citation Graph (0, 0)][DBLP]
   Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:813-830 [Journal]
   
10. Yi-Sheng Zhu, Ru-Lai Li, Wai-Kai Chen
    Design of High-pass Impedance-matching Networks with Series Rc Load. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:831-840 [Journal]
    
11. C. Charopoulos, Fotis Andritsopoulos, Yannis Mitsos, Gregory Doumenis, G. Stasinopoulos
    Packet Indexing Process Optimized for High-speed Network Processors. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:841-860 [Journal]
    
12. Joung-Youn Kim, Lee-Sup Kim
    An Efficient Memory Address Converter for Soc-based 3d Graphics System. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:861-876 [Journal]
    
13. Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Constantinos E. Goutis
    A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels. [Citation Graph (0, 0)][DBLP]
    Journal of Circuits, Systems, and Computers, 2005, v:14, n:4, pp:877-893 [Journal]