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Journals in DBLP

J. Instruction-Level Parallelism
2000, volume: 2, number:

  1. David H. Albonesi
    Selective Cache Ways: On-Demand Cache Resource Allocation. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  2. Zheng Wang, Ken Pierce, Scott McFarling
    BMAT - A Binary Matching Tool for Stale Profile Propagation. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  3. Ilan Y. Spillinger, Chris J. Newburn
    Guest Editors' Introduction. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  4. Kevin Skadron, Margaret Martonosi, Douglas W. Clark
    Speculative Updates of Local and Global Branch History: A Quantitative Analysis. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  5. Serap A. Savari, Cliff Young
    Comparing and Combining Profiles. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  6. Eric Rotenberg, James E. Smith
    Control Independence in Trace Processors. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  7. Vijay S. Pai, Sarita V. Adve
    Code Transformations to Improve Memory Parallelism. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  8. Andreas Moshovos, Gurindar S. Sohi
    Memory Dependence Prediction in Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  9. Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
    Dynamic Register Renaming Through Virtual-Physical Registers. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  10. Robert S. Cohn, P. Geoffrey Lowney
    Design and Analysis of Profile-Based Optimization in Compaq's Compilation Tools for Alpha. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  11. Brad Calder, Glenn Reinman
    A Comparative Survey of Load Speculation Architectures. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  12. Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey
    Wavefront Scheduling: Path Based Data Representation and Scheduling of Subgraphs. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  13. Todd M. Austin
    DIVA: A Dynamic Approach to Microprocessor Verification. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
  14. Andrew Wolfe, Derek B. Noonburg
    A Superscalar 3D Graphics Engine. [Citation Graph (0, 0)][DBLP]
    J. Instruction-Level Parallelism, 2000, v:2, n:, pp:- [Journal]
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