Journals in DBLP

J. Inf. Sci. Eng.
2000, volume: 16, number: 5

1. Angela Krstic, Srimat T. Chakradhar, Kwang-Ting Cheng
   Testable Path Delay Fault Cover for Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:673-686 [Journal]
   
2. Hsing-Chung Liang, Chung-Len Lee
   Flip-Flop Selection for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:687-702 [Journal]
   
3. Elizabeth M. Rudnick, Miron Abramovici
   Compact Test Generation Using a Frozen Clock Testing Strategy. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:703-717 [Journal]
   
4. Sying-Jyan Wang, Chia-Chun Lien
   Testability Improvement by Branch Point Control for Conditional Staements With Multiple Branches. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:719-731 [Journal]
   
5. Shyue-Kung Lu, Jen-Sheng Shih
   Testing Configurable LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:733-750 [Journal]
   
6. Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su
   A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:751-766 [Journal]
   
7. Chauchin Su, Yue-Tsang Chen, Shenshung Chiang
   Impulse Response Fault Model and Fault Extraction for Functional Level Analog Circuit Diagnosis. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:767-781 [Journal]
   
8. Chih-Yuang Su, Cheng-Wen Wu
   A Probabilistic Model for Path Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
   J. Inf. Sci. Eng., 2000, v:16, n:5, pp:783-794 [Journal]