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Journals in DBLP

J. Inf. Sci. Eng.
1998, volume: 14, number: 1

  1. Jing-Chiou Liou, Michael A. Palis
    On the Effectiveness of Compiler-Time Scheduling Approaches for Distributed Memory Multiprocessor. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:7-26 [Journal]
  2. S. K. S. Gupta, S. Drishnamurthy
    An Interprocedural Framework for Determining Efficient Array Data Redistributeions. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:27-51 [Journal]
  3. Chien-Min Wang, Yomin Hou, Chiu-Yu Ku
    Compiler Techniques for Minimizing Link Contention of Linear-Constant Communication on k-ary n-cubes. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:53-78 [Journal]
  4. Pangfeng Liu, Jan-Jan Wu
    Supporting Efficieent Tree Structures for Distributed Scientific Computation. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:79-105 [Journal]
  5. Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Meenakshi A. Kandaswamy
    Locality Optimization Algorithms for Compilation of Out-of-Core Codes. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:107-138 [Journal]
  6. Yin-Tsung Hwang, Jer-Sho Hwang
    Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:139-165 [Journal]
  7. Frederic Desprez, Jack Dongarra, Fabrice Rastello, Yves Robert
    Determining the Idle Time of a Tiling: New Results. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:167-190 [Journal]
  8. Beniamino Di Martino
    Algorithmic Concept Recognition Support for Automatic Parallelization: A Case Study on Loop Optimization and Parallelization. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:191-203 [Journal]
  9. Jenn-Yuan Tsai, Zhenzhen Jiang, Zhiyuan Li, David J. Lilja, Xin Wang, Pen-Chung Yew, Bixia Zheng, Stephen J. Schwinn
    Integrating Parallelizing Compilation Technology and Processor Architecture for Cost-Effective Concurrent multithreading. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:205-222 [Journal]
  10. Sangho Ha, Heunghwan Kim
    KU-Loop Scheme: An Efficient Loop Unfolding Scheme for Multithreaded Computation. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:223-236 [Journal]
  11. Chao-Tung Yang, Shian-Shyong Tseng, Ming-Huei Hsieh, Shih-Hung Kao
    Efficient Run-Time Parallelization for DO Loops. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:237-253 [Journal]
  12. Tsung-Chuan Huang, Po-Hsueh Hsu, Tze-Nan Sheng
    Efficient Run-Time Scheduling for Parallelizing Partially Parallel Loops. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:255-264 [Journal]
  13. Fermín Sánchez, Jordi Cortadella
    Reducing Register Pressure in Software Pipelining. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:265-279 [Journal]
  14. Sheng-De Wang, Wei-Der Jwo
    Replication and Partitioning for Data Arrays in Distributed Memory Systems. [Citation Graph (0, 0)][DBLP]
    J. Inf. Sci. Eng., 1998, v:14, n:1, pp:281-298 [Journal]
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