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Journals in DBLP

Journal of Systems Architecture
2003, volume: 49, number: 12-15

  1. Martyn Edwards, Lech Józwiak
    Preface. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:485-487 [Journal]
  2. Krzysztof Kuchcinski, Christophe Wolinski
    Global approach to assignment and scheduling of complex behaviors based on HCDG and constraint programming. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:489-503 [Journal]
  3. María C. Molina, José M. Mendías, Román Hermida
    Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:505-519 [Journal]
  4. Rolf Drechsler, Wolfgang Günther, Thomas Eschbach, Lothar Linhard, Gerhard Angst
    Recursive bi-partitioning of netlists for large number of partitions. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:521-528 [Journal]
  5. Enrique San Millán, Luis Entrena, José Alberto Espejo, Celia López
    Theoretical comparison between sequential redundancy addition and removal and retiming optimization techniques. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:529-541 [Journal]
  6. D. Piso, José-Alejandro Piñeiro, Javier D. Bruguera
    Analysis of the impact of different methods for division/square root computation in the performance of a superscalar microprocessor. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:543-555 [Journal]
  7. Colin Egan, Gordon Steven, Patrick Quick, Rubén Anguera, Fleur Steven, Lucian N. Vintan
    Two-level branch prediction using neural networks. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:557-570 [Journal]
  8. Luis Alejandro Cortés, Petru Eles, Zebo Peng
    Modeling and formal verification of embedded systems based on a Petri net representation. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:571-598 [Journal]
  9. Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff
    Implementation of a streaming execution unit. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:599-617 [Journal]
  10. Bart D. Theelen, A. C. Verschueren, V. V. Reyes Suárez, M. P. J. Stevens, A. Nuñez
    A scalable single-chip multi-processor architecture with on-chip RTOS kernel. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:619-639 [Journal]
  11. Matías J. Garrido, César Sanz, Marcos Jiménez, Juan M. Meneses
    A flexible architecture for H.263 video coding. [Citation Graph (0, 0)][DBLP]
    Journal of Systems Architecture, 2003, v:49, n:12-15, pp:641-661 [Journal]
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