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Journals in DBLP
IEEE Micro 2003, volume: 23, number: 6
Letters. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:5- [Journal]
- Charles R. Moore, Kevin W. Rudd, Ruby B. Lee, Pradip Bose
Guest Editors' Introduction: Micro's Top Picks from Microarchitecture Conferences. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:8-10 [Journal]
- Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan
Checkpoint Processing and Recovery: An Efficient, Scalable Alternative to Reorder Buffers. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:11-19 [Journal]
- Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt
Runahead Execution: An Effective Alternative to Large Instruction Windows. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:20-25 [Journal]
- Michael K. Chen, Kunle Olukotun
The Jrpm System for Dynamically Parallelizing Sequential Java Programs. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:26-35 [Journal]
- Christoforos E. Kozyrakis, David A. Patterson
Scalable Vector Processors for Embedded Systems. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:36-45 [Journal]
- Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:46-51 [Journal]
- Kevin Skadron, Mircea R. Stan, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan
Temperature-Aware Computer Systems: Opportunities and Challenges. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:52-61 [Journal]
- Grigorios Magklis, Greg Semeraro, David H. Albonesi, Steve Dropsho, Sandhya Dwarkadas, Michael L. Scott
Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:62-68 [Journal]
- Shubhendu S. Mukherjee, Chris Weaver, Joel S. Emer, Steven K. Reinhardt, Todd M. Austin
Measuring Architectural Vulnerability Factors. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:70-75 [Journal]
- Mohamed A. Gomaa, Chad Scarbrough, T. N. Vijaykumar, Irith Pomeranz
Transient-Fault Recovery for Chip Multiprocessors. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:76-83 [Journal]
- Timothy Sherwood, Erez Perelman, Greg Hamerly, Suleyman Sair, Brad Calder
Discovering and Exploiting Program Phases. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:84-93 [Journal]
- Alaa R. Alameldeen, David A. Wood
Addressing Workload Variability in Architectural Simulations. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:94-98 [Journal]
- Changkyu Kim, Doug Burger, Stephen W. Keckler
Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:99-107 [Journal]
- Milo M. K. Martin, Mark D. Hill, David A. Wood
Token Coherence: A New Framework for Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:108-116 [Journal]
- Ravi Rajwar, James A. Goodman
Transactional Execution: Toward Reliable, High-Performance Multithreading. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:117-125 [Journal]
- José F. Martínez, Josep Torrellas
Speculative Synchronization: Programmability and Performance for Parallel Codes. [Citation Graph (0, 0)][DBLP] IEEE Micro, 2003, v:23, n:6, pp:126-134 [Journal]
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