Journals in DBLP

SIGARCH Computer Architecture News
2003, volume: 31, number: 1

1. Jack B. Dennis
   Fresh Breeze: a multiprocessor chip architecture guided by modular programming principles. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:7-15 [Journal]
   
2. David Morano, Alireza Khalafi, David R. Kaeli, Augustus K. Uht
   Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:16-25 [Journal]
   
3. George Almási, Calin Cascaval, José G. Castaños, Monty Denneau, Derek Lieber, José E. Moreira, Henry S. Warren Jr.
   Dissecting Cyclops: a detailed analysis of a multithreaded architecture. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:26-38 [Journal]
   
4. Mohamed M. Zahran
   On cache memory hierarchy for Chip-Multiprocessor. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:39-48 [Journal]
   
5. Gary Gréwal, Tom Wilson, Andrew Morton
   An EGA approach to the compile-time assignment of data to multiple memories in digital-signal processors. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:49-59 [Journal]
   
6. Ulrich Ramacher, Nico Brüls, J. A. Ulrich Hachmann, Jens Harnisch, Wolfgang Raab, Axel Techmer
   100 GOPS vision processor for automotive applications. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:60-68 [Journal]
   
7. Nikos Pitsianis, Gerald G. Pechanek
   Indirect VLIW memory allocation for the ManArray multiprocessor DSP. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:69-74 [Journal]
   
8. Naohiko Shimizu, Ken Takatori
   A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:75-84 [Journal]
   
9. Alessio Bechini, Pierfrancesco Foglia, Cosimo Antonio Prete
   Fine-grain design space exploration for a cartographic SoC multiprocessor. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:85-92 [Journal]
   
10. Mark Thorson
    Internet nuggets. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2003, v:31, n:1, pp:93-96 [Journal]