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Journals in DBLP

SIGARCH Computer Architecture News
2005, volume: 33, number: 3

  1. Sandro Bartolini, Pierfrancesco Foglia, Cosimo Antonio Prete
    Guests editor's introduction. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:1-2 [Journal]
  2. Hanene Ben Fradj, Asmaa el Ouardighi, Cécile Belleudy, Michel Auguin
    Energy aware memory architecture configuration. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:3-9 [Journal]
  3. Hyo-Joong Suh, Sung Woo Chung
    DRACO: optimized CC-NUMA system with novel dual-link interconnections to reduce the memory latency. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:10-16 [Journal]
  4. Sami Yehia, Jean-Francois Collard, Olivier Temam
    Load squared: adding logic close to memory to reduce the latency of indirect loads with high miss ratios. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:17-24 [Journal]
  5. Hiroaki Kobayashi, Isao Kotera, Hiroyuki Takizawa
    Locality analysis to control dynamically way-adaptable caches. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:25-32 [Journal]
  6. Fumio Arakawa, Makoto Ishikawa, Yuki Kondo, Tatsuya Kamei, Motokazu Ozawa, Osamu Nishii, Toshihiro Hattori
    SH-X: an embedded processor core for consumer appliances. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:33-40 [Journal]
  7. Afrin Naz, Mehran Rezaei, Krishna M. Kavi, Philip H. Sweany
    Improving data cache performance with integrated use of split caches, victim cache and stream buffers. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:41-48 [Journal]
  8. Alex Pajuelo, Antonio González, Mateo Valero
    Speculative execution for hiding memory latency. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:49-56 [Journal]
  9. Javier Verdú, Jorge García, Mario Nemirovsky, Mateo Valero
    The impact of traffic aggregation on the memory performance of networking applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:57-62 [Journal]
  10. Bramha Allu, Wei Zhang 0002
    Exploiting the replication cache to improve performance for multiple-issue microprocessors. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:63-71 [Journal]
  11. Mark Thorson
    Internet nuggets. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2005, v:33, n:3, pp:72-74 [Journal]
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