Journals in DBLP

SIGARCH Computer Architecture News
2004, volume: 32, number: 3

1. Adrián Cristal, José F. Martínez, Josep Llosa, Mateo Valero
   A case for resource-conscious out-of-order processors: towards kilo-instruction in-flight processors. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:3-10 [Journal]
   
2. Partha Kundu, Murali Annavaram, Trung A. Diep, John Shen
   A case for shared instruction cache on chip multiprocessors running OLTP. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:11-18 [Journal]
   
3. Nagarajan Venkateswaran, Aditya Krishnan, S. Niranjan Kumar, Arrvindh Shriraman, Srinivas Sridharan
   Memory in processor: a novel design paradigm for supercomputing architectures. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:19-26 [Journal]
   
4. Irina Branovic, Roberto Giorgi, Enrico Martinelli
   A workload characterization of elliptic curve cryptography methods in embedded environments. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:27-34 [Journal]
   
5. K. Brifault, Henri-Pierre Charles
   Data cache management on EPIC architecture: optimizing memory access for image processing. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:35-42 [Journal]
   
6. Naohiko Shimizu, Chiaki Kon
   Java object look aside buffer for embedded applications. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:43-49 [Journal]
   
7. Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato
   A leakage-energy-reduction technique for highly-associative caches in embedded systems. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:50-54 [Journal]
   
8. Sören Moch, Mladen Berekovic, Hans-Joachim Stolberg, Lars Friebe, Mark Bernd Kulaczewski, A. Dehnhardt, Peter Pirsch
   HIBRID-SOC: a multi-core architecture for image and video applications. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:55-61 [Journal]
   
9. Mladen Berekovic, Sören Moch, Peter Pirsch
   A scalable, clustered SMT processor for digital signal processing. [Citation Graph (0, 0)][DBLP]
   SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:62-69 [Journal]
   
10. Sandro Bartolini, Cosimo Antonio Prete
    A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:70-77 [Journal]
    
11. Mark Thorson
    Internet nuggets. [Citation Graph (0, 0)][DBLP]
    SIGARCH Computer Architecture News, 2004, v:32, n:3, pp:78-83 [Journal]