The SCEAS System
Navigation Menu

Journals in DBLP

STTT
2001, volume: 3, number: 3

  1. Rance Cleaveland
    Alternative Approaches to Symbolic Verification - Preface by the Section Editor. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:247-249 [Journal]
  2. Giorgio Delzanno, Andreas Podelski
    Constraint-based deductive model checking. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:250-270 [Journal]
  3. Daniel Hirschkoff
    Bisimulation verification using the up to techniques. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:271-285 [Journal]
  4. Christoph Kern, Tarik Ono-Tesfaye, Mark R. Greenstreet
    A light-weight framework for hardware verification. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:286-313 [Journal]
  5. Hubert Garavel, César Viho, Massimo Zendri
    System design of a CC-NUMA multiprocessor architecture using formal specification, model-checking, co-simulation, and test generation. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:314-331 [Journal]
  6. Marieke Huisman, Bart Jacobs, Joachim van den Berg
    A case study in class library verification: Java's vector class. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:332-352 [Journal]
  7. Magnus Lindahl, Paul Pettersson, Wang Yi
    Formal design and analysis of a gear controller. [Citation Graph (0, 0)][DBLP]
    STTT, 2001, v:3, n:3, pp:353-368 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002