Journals in DBLP

IEEE Trans. Computers
2001, volume: 50, number: 11

1. Haldun Hadimioglu, David R. Kaeli, Fabrizio Lombardi
   Introduction to the Special Section on High Performance Memory Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1103-1104 [Journal]
   
2. Maurice V. Wilkes
   High Performance Memory Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1105- [Journal]
   
3. Caroline Benveniste, Peter A. Franaszek, John T. Robinson
   Cache-Memory Interfaces in Compressed Memory Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1106-1116 [Journal]
   
4. Lixin Zhang, Zhen Fang, Michael Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee
   The Impulse Memory Controller. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1117-1132 [Journal]
   
5. Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge
   High-Performance DRAMs in Workstation Environments. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1133-1153 [Journal]
   
6. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin
   Hardware and Software Techniques for Controlling DRAM Power Modes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1154-1173 [Journal]
   
7. Kevin M. Lepak, Gordon B. Bell, Mikko H. Lipasti
   Silent Stores and Store Value Locality. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1174-1190 [Journal]
   
8. Rui Min, Yiming Hu
   Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1191-1201 [Journal]
   
9. Wei-Fen Lin, Steven K. Reinhardt, Doug Burger
   Designing a Modern Memory Hierarchy with Hardware Prefetching. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2001, v:50, n:11, pp:1202-1218 [Journal]
   
10. Bülent Abali, Mohammad Banikazemi, Xiaowei Shen, Hubertus Franke, Dan E. Poff, T. Basil Smith
    Hardware Compressed Main Memory: Operating System Support and Performance Evaluation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1219-1233 [Journal]
    
11. Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal
    Compiler Support for Scalable and Efficient Memory Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1234-1247 [Journal]
    
12. Yan Solihin, Jaejin Lee, Josep Torrellas
    Automatic Code Mapping on an Intelligent Memory Architecture. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1248-1266 [Journal]
    
13. Dhananjay S. Phatak, Tom Goff, Israel Koren
    Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1267-1278 [Journal]
    
14. Annie A. M. Cuyt, R. B. Lenin
    Multivariate Rational Approximants for Multiclass Closed Queuing Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1279-1288 [Journal]
    
15. Jawahar Jain, Ingo Wegener, Masahiro Fujita
    A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1289-1290 [Journal]
    
16. Mao-Hsu Yen, Sao-Jie Chen, Sanko Lan
    A Three-Stage One-Sided Rearrangeable Polygonal Switching Network. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2001, v:50, n:11, pp:1291-1294 [Journal]