Journals in DBLP

IEEE Trans. Computers
2004, volume: 53, number: 11

1. Peter Y. K. Cheung, George A. Constantinides, José T. de Sousa
   Guest Editors' Introduction: Field Programmable Logic and Applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1361-1362 [Journal]
   
2. Stamatis Vassiliadis, Stephan Wong, Georgi Gaydadjiev, Koen Bertels, Georgi Kuzmanov, Elena Moscu Panainte
   The MOLEN Polymorphic Processor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1363-1375 [Journal]
   
3. John Teifel, Rajit Manohar
   An Asynchronous Dataflow FPGA Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1376-1392 [Journal]
   
4. Christoph Steiger, Herbert Walder, Marco Platzner
   Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-Time Tasks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1393-1407 [Journal]
   
5. Henry Styles, Wayne Luk
   Exploiting Program Branch Probabilities in Hardware Compilation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1408-1419 [Journal]
   
6. Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee
   Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1420-1435 [Journal]
   
7. Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu
   Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1436-1448 [Journal]
   
8. Iouliia Skliarova, António de Brito Ferrari
   Reconfigurable Hardware SAT Solvers: A Survey of Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1449-1461 [Journal]
   
9. Enrico Bini, Giorgio C. Buttazzo
   Schedulability Analysis of Periodic Fixed Priority Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2004, v:53, n:11, pp:1462-1473 [Journal]
   
10. Dan Page, Nigel P. Smart
    Parallel Cryptographic Arithmetic Using a Redundant Montgomery Representation. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1474-1482 [Journal]
    
11. Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey
    Efficient Design Diversity Estimation for Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1483-1492 [Journal]
    
12. Feng Bao
    Cryptanalysis of a Partially Known Cellular Automata Cryptosystem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1493-1497 [Journal]
    
13. Irith Pomeranz, Sudhakar M. Reddy
    A Measure of Quality for n-Detection Test Sets. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2004, v:53, n:11, pp:1497-1503 [Journal]