Journals in DBLP

IEEE Trans. Computers
1976, volume: 25, number: 6

1. William C. Carter, Charles E. McCarthy
   Implementation of an Experimental Fault-Tolerant Memory System. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:557-568 [Journal]
   
2. Jacques Losq
   A Highly Efficient Redundancy Scheme: Self-Purging Redundancy. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:569-578 [Journal]
   
3. John F. Meyer
   Computation-Based Reliability Analysis. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:578-584 [Journal]
   
4. Ferruccio Barsi, Fabrizio Grandoni 0002, Piero Maestrini
   A Theory of Diagnosability of Digital Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:585-593 [Journal]
   
5. Ramachendra P. Batni, Charles R. Kime
   A Module-Level Testing Approach for Combinational Networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:594-604 [Journal]
   
6. Francisco J. O. Dias
   Truth-Table Verification of an Iterative Logic Array. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:605-613 [Journal]
   
7. John P. Hayes
   Transition Count Testing of Combinational Logic Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:613-620 [Journal]
   
8. Sheldon B. Akers Jr.
   A Logic System for Fault Test Generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:620-630 [Journal]
   
9. Peter Muth
   A Nine-Valued Circuit Model for Test Generation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1976, v:25, n:6, pp:630-636 [Journal]
   
10. Henry Y. H. Chuang
    Fail-Safe Asynchronous Machines with Multiple-Input Changes. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:637-642 [Journal]
    
11. P. Prusinkiewicz, S. Budkowski
    A Double Track Error-Correction Code for Magnetic Tape. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:642-645 [Journal]
    
12. Chantal Robach, Gabriele Saucier, J. Lebrun
    Processor Testability and Design Consequences. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:645-652 [Journal]
    
13. Claudine Turcat, André Verdillon
    Recursion and Testing of Combinational Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:652-659 [Journal]
    
14. René David, Gérard Blanchet
    About Random Fault Detection of Combinational Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:659-664 [Journal]
    
15. Prathima Agrawal, Vishwani D. Agrawal
    On Monte Carlo Testing of Logic Tree Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1976, v:25, n:6, pp:664-667 [Journal]