The SCEAS System
Navigation Menu

Journals in DBLP

IEEE Trans. Computers
1992, volume: 41, number: 7

  1. Anoop Gupta, Wolf-Dietrich Weber
    Cache Invalidation Patterns in Shared-Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:794-810 [Journal]
  2. Jaswinder Pal Singh, Harold S. Stone, Dominique Thiébaut
    A Model of Workloads and Its Use in Miss-Rate Prediction for Fully Associative Caches. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:811-825 [Journal]
  3. Augustus K. Uht
    Concurrency Extraction via Hardware Methods Executing the Static Instruction Stream. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:826-841 [Journal]
  4. Anindo Bagchi, S. Louis Hakimi
    Data Transfers in Broadcast Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:842-847 [Journal]
  5. Miguel Angel Fiol, Anna S. Lladó
    The Partial Line Digraph Technique in the Design of Large Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:848-857 [Journal]
  6. Morteza Afghahi, Christer Svensson
    Performance of Synchronous and Asynchronous Schemes for VLSI Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:858-872 [Journal]
  7. Ching-Tien Ho
    An Observation on the Bisectional Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:873-877 [Journal]
  8. Cheol-Hoon Lee, Dongmyun Lee, Myunghwan Kim
    Optimal Task Assignment in Linear Array Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:877-880 [Journal]
  9. D. L. Tao, Carlos R. P. Hartmann, Parag K. Lala
    A General Technique for Designing Totally Self-Checking Checker for 1-out-of-N Code with Minimum Gate Delay. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:881-886 [Journal]
  10. Naofumi Takagi, Shuzo Yajima
    Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:887-891 [Journal]
  11. Nick Kanopoulos, Dimitris Pantzartzis, Frederick R. Bartram
    Design of Self-Checking Circuits Using DCVS Logic: A Case Study. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:891-896 [Journal]
  12. Andrea S. LaPaugh, Richard J. Lipton, Jonathan S. Sandberg
    How to Store a Triangular Matrix. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:896-899 [Journal]
  13. Arun K. Somani, Vinod K. Agarwal
    Distributed Diagnosis Algorithms for Regular Interconnected Structures. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:899-906 [Journal]
  14. Anastasios Vergis
    On the Testability of One-Dimensional ILA's for Multiple Sequential Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:7, pp:906-916 [Journal]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002