Journals in DBLP

IEEE Trans. Computers
1992, volume: 41, number: 10

1. Isaac D. Scherson, David A. Kramer, Brian D. Alleyne
   Bit-Parallel Arithmetic in a Massively-Parallel Associative Processor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1201-1210 [Journal]
   
2. Hans Mulder, Michael J. Flynn
   Processor Architecture and Data Buffering. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1211-1222 [Journal]
   
3. Patrick W. Dowd
   Wavelength Division Multiple Access Channel Hypercube Processor Interconnection. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1223-1241 [Journal]
   
4. Tze Chiang Lee, John P. Hayes
   A Fault-Tolerant Communication Scheme for Hypercube Computers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1242-1256 [Journal]
   
5. Dilip D. Kandlur, Kang G. Shin
   Traffic Routing for Multicomputer Networks with Virtual Cut-Through Capability. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1257-1270 [Journal]
   
6. Philippe Nain, Donald F. Towsley
   Comparison of Hybrid Minimum Laxity/First-In-First-Out Scheduling Policies for Real-Time Multiprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1271-1278 [Journal]
   
7. Robert F. Berry
   Computer Benchmark Evaluation and Design of Experiments, a Case Study. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1279-1289 [Journal]
   
8. Randy Allen, Ken Kennedy
   Vector Register Allocation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1290-1317 [Journal]
   
9. Jehoshua Bruck, Mario Blaum
   New Techniques for Constructing EC/AUED Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1992, v:41, n:10, pp:1318-1324 [Journal]
   
10. Ronald J. Cosentino, John J. Vaccaro
    Adaptation of the Mactaggart and Jack Complex Multiplication Algorithm for Floating-Point Operators. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1324-1326 [Journal]
    
11. Kwang Soo Hong, Joseph Y.-T. Leung
    On-Line Scheduling of Real-Time Tasks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1326-1331 [Journal]
    
12. Alexander Skavantzos, Thanos Stouraitis
    Decomposition of Complex Multipliers Using Polynomial Encoding. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1331-1333 [Journal]
    
13. Y. C. Lim
    Single-Precision Multiplier with Reduced Circuit Complexity for Signal Processing Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1333-1336 [Journal]
    
14. Brian Alspach
    Cayley Graphs with Optimal Fault Tolerance. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1337-1339 [Journal]
    
15. Fabrizio Lombardi, Chao Feng, Wei-Kang Huang
    Detection and Location of Multiple Faults in Baseline Interconnection Networks. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1340-1344 [Journal]
    
16. Sterling R. Whitaker, Gary K. Maki
    Self Synchronized Asynchronous Sequential Pass Transistor Circuits. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1992, v:41, n:10, pp:1344-1348 [Journal]