Journals in DBLP

IEEE Trans. Computers
1986, volume: 35, number: 1

1. Dan I. Moldovan, José A. B. Fortes
   Partitioning and Mapping Algorithms into Fixed Size Systolic Arrays. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:1-12 [Journal]
   
2. Anastasios Vergis, Kenneth Steiglitz
   Testability Conditions for Bilateral Arrays of Combinational Cells. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:13-22 [Journal]
   
3. Iiro Hartimo, Klaus Kronlöf, Olli Simula, Jorma Skyttä
   DFSP: A Data Flow Signal Processor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:23-33 [Journal]
   
4. Avinoam Bilgory, Daniel Gajski
   A Heuristic for Suffix Solutions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:34-42 [Journal]
   
5. David Lee Tuomenoksa, Howard Jay Siegel
   Determining an Optimal Secondary Storage Service Rate for the PASM Control System. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:43-53 [Journal]
   
6. Peter G. Harrison
   An Enhanced Approximation by Pair-Wise Analysis of Servers for Time Delay Distributions in Queueing Networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:54-61 [Journal]
   
7. Alok Aggarwal
   Optimal Bounds for Finding Maximum on Array of Processors with k Global Buses. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:62-64 [Journal]
   
8. Jacob Savir
   The Bidirectional Double Latch (BDDL). [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:65-66 [Journal]
   
9. J. Calvo, J. I. Acha, Manuel Valencia
   Asynchronous Modular Arbiter. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1986, v:35, n:1, pp:67-70 [Journal]
   
10. Füsun Özgüner
    Deductive Fault Simulation of Internal Faults of Inverter-Free Circuits and Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:70-73 [Journal]
    
11. Michael Journeau
    A Note on the Restricted Range Cutting Algorithm. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:73- [Journal]
    
12. Concettina Guerra
    Systolic Algorithms for Local Operations on Images. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:73-77 [Journal]
    
13. Louise Trevillyan, William H. Joyner Jr., C. Leonard Berman
    Global Flow Analysis in Automatic Logic Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:77-81 [Journal]
    
14. Janusz Rajski, Jerzy Tyszer
    The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:81-85 [Journal]
    
15. Bhargab B. Bhattacharya, Bidyut Gupta
    On the Impossible Class of Faulty Functions in Logic Networks Under Short Circuit Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:85-90 [Journal]
    
16. Abhijit Sengupta, Arunabha Sen, Subir Bandyopadhyay
    On System Diagnosability in the Presence of Hybrid Faults. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:90-93 [Journal]
    
17. Israel Koren
    Comments on ``The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1986, v:35, n:1, pp:93-94 [Journal]