Journals in DBLP

IEEE Trans. Computers
2005, volume: 54, number: 7

1. Viktor K. Prasanna
   Editor's Note. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:785-787 [Journal]
   
2. Robert B. Reese, Mitchell A. Thornton, Cherrice Traver
   A Coarse-Grain Phased Logic CPU. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:788-799 [Journal]
   
3. Hans Vandierendonck, Koenraad De Bosschere
   XOR-Based Hash Functions. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:800-812 [Journal]
   
4. Haibin Lu, Sartaj Sahni
   A B-Tree Dynamic Router-Table Design. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:813-824 [Journal]
   
5. Eric M. Schwarz, Martin S. Schmookler, Son Dao Trong
   FPU Implementations with Denormalized Numbers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:825-836 [Journal]
   
6. Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
   Digit-Recurrence Dividers with Reduced Logical Depth. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:837-851 [Journal]
   
7. Robert Granger, Dan Page, Martijn Stam
   Hardware and Software Normal Basis Arithmetic for Pairing-Based Cryptography in Characteristic Three. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:852-860 [Journal]
   
8. Thomas J. Wollinger, Jan Pelzl, Christof Paar
   Cantor versus Harley: Optimization and Analysis of Explicit Formulae for Hyperelliptic Curve Cryptosystems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:861-872 [Journal]
   
9. Xuehong Sun, Yiqiang Q. Zhao
   An On-Chip IP Address Lookup Algorithm. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:7, pp:873-885 [Journal]
   
10. Sanghamitra Roy, Prith Banerjee
    An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:886-896 [Journal]
    
11. Huiyang Zhou, Thomas M. Conte
    Enhancing Memory-Level Parallelism via Recovery-Free Value Prediction. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:897-912 [Journal]
    
12. André Seznec, Roger Espasa
    Conflict-Free Accesses to Strided Vectors on a Banked Cache. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:913-196 [Journal]
    
13. Byeong Kil Lee, Lizy Kurian John
    Implications of Executing Compression and Encryption Applications on General Purpose Processors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:917-922 [Journal]
    
14. Carlos Álvarez, Jesús Corbal, Mateo Valero
    Fuzzy Memoization for Floating-Point Multimedia Applications. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2005, v:54, n:7, pp:922-927 [Journal]