Journals in DBLP

IEEE Trans. Computers
2006, volume: 55, number: 3

1. Viktor K. Prasanna
   Editor's Note. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:241-242 [Journal]
   
2. Wu Jigang, Thambipillai Srikanthan
   Reconfiguration Algorithms for Power Efficient VLSI Subarrays with Four-Port Switches. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:243-253 [Journal]
   
3. Julio Villalba, Tomás Lang, Mario A. González
   Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:254-267 [Journal]
   
4. Joshua J. Yi, David J. Lilja
   Simulation of Computer Architectures: Simulators, Benchmarks, Methodologies, and Recommendations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:268-280 [Journal]
   
5. Juan L. Aragón, José M. González, Antonio González
   Control Speculation for Energy-Efficient Next-Generation Superscalar Processors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:281-291 [Journal]
   
6. Stephen Paynter, Neil Henderson, James M. Armstrong
   Metastability in Asynchronous Wait-Free Protocols. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:292-303 [Journal]
   
7. Mehdi Amirijoo, Jörgen Hansson, Sang Hyuk Son
   Specification and Management of QoS in Real-Time Databases Supporting Imprecise Computations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:304-319 [Journal]
   
8. Donglin Liu, Xiaobo Sharon Hu, Michael D. Lemmon, Qiang Ling
   Firm Real-Time System Scheduling Based on a Novel QoS Constraint. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:320-333 [Journal]
   
9. Jie Wu, Wei Lou, Fei Dai
   Extended Multipoint Relays to Determine Connected Dominating Sets in MANETs. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2006, v:55, n:3, pp:334-347 [Journal]
   
10. Michele Favalli
    Diversity Analysis in the Presence of Delay Faults Affecting Duplex Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 2006, v:55, n:3, pp:348-352 [Journal]