Journals in DBLP
Régis Leveugle , Gabriele Saucier Optimized Synthesis of Concurrently Checked Controllers. [Citation Graph (0, 0)][DBLP ] Journal ] V. S. S. Nair , Jacob A. Abraham Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. [Citation Graph (0, 0)][DBLP ] Journal ] Vijay Balasubramanian , Prithviraj Banerjee Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors. [Citation Graph (0, 0)][DBLP ] Journal ] Mahadev Satyanarayanan , James J. Kistler , Puneet Kumar , Maria E. Okasaki , Ellen H. Siegel , David C. Steere Coda: A Highly Available File System for a Distributed Workstation Environment. [Citation Graph (16, 0)][DBLP ] Journal ] Kun-Lung Wu , W. Kent Fuchs Recoverable Distributed Shared Virtual Memory. [Citation Graph (2, 0)][DBLP ] Journal ] Dong Sam Ha , Vijay P. Kumar On the Design of High-Yield Reconfigurable PLA's. [Citation Graph (0, 0)][DBLP ] Journal ] Vwani P. Roychowdhury , Jehoshua Bruck , Thomas Kailath Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP ] Journal ] Shantanu Dutt , John P. Hayes On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. [Citation Graph (0, 0)][DBLP ] Journal ] Jean Arlat , Karama Kanoun , Jean-Claude Laprie Dependability Modeling and Evaluation of Software Fault-Tolerant Systems. [Citation Graph (0, 0)][DBLP ] Journal ] Parameswaran Ramanathan , Dilip D. Kandlur , Kang G. Shin Hardware-Assisted Software Clock Synchronization for Homogeneous Distributed Systems. [Citation Graph (1, 0)][DBLP ] Journal ] Ravishankar K. Iyer , Luke T. Young , P. V. Krishna Iyer Automatic Recognition of Intermittent Failures: An Experimental Study of Field Data. [Citation Graph (0, 0)][DBLP ] Journal ] Rajesh Gupta , Rajiv Gupta , Melvin A. Breuer The BALLAST Methodology for Structured Partial Scan Design. [Citation Graph (0, 0)][DBLP ] Journal ] Kwang-Ting Cheng , Vishwani D. Agrawal A Partial Scan Method for Sequential Circuits with Feedback. [Citation Graph (0, 0)][DBLP ] Journal ] Yuval Tamir , Marc Tremblay High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback. [Citation Graph (0, 0)][DBLP ] Journal ] Nirmal R. Saxena , Edward J. McCluskey Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. [Citation Graph (0, 0)][DBLP ] Journal ] Ming-Feng Chang , Weiping Shi , W. Kent Fuchs Optimal Diagnosis Procedures for k-out-of-n Structures. [Citation Graph (0, 0)][DBLP ] Journal ] Mengly Chean , José A. B. Fortes The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays. [Citation Graph (0, 0)][DBLP ] Journal ] Meera Balakrishnan , C. S. Raghavendra On Reliability Modeling of Closed Fault-Tolerant Computer Systems. [Citation Graph (0, 0)][DBLP ] Journal ] James H. Barton , Edward W. Czeck , Zary Segall , Daniel P. Siewiorek Fault Injection Experiments Using FIAT. [Citation Graph (2, 0)][DBLP ] Journal ] Sharad C. Seth , Vishwani D. Agrawal , Hassan Farhat A Statistical Theory of Digital Circuit Testability. [Citation Graph (0, 0)][DBLP ] Journal ] Dhiraj K. Pradhan , Sandeep K. Gupta , Mark G. Karpovsky Aliasing Probability for Multiple Input Signature Analyzer. [Citation Graph (0, 0)][DBLP ] Journal ] Larry A. Dunning , Gur Dial , Murali R. Varanasi Unidirectional Byte Error Detecting Codes for Computer Memory Systems. [Citation Graph (0, 0)][DBLP ] Journal ] 