Journals in DBLP

IEEE Trans. Computers
1990, volume: 39, number: 3

1. Ahmed E. Kamal, V. Carl Hamacher
   Utilizing Bandwidth Sharing in the Slotted Ring. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:289-299 [Journal]
   
2. Arvind, Rishiyur S. Nikhil
   Executing a Program on the MIT Tagged-Token Dataflow Architecture. [Citation Graph (1, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:300-318 [Journal]
   
3. Hyunsoo Yoon, Kyungsook Y. Lee, Ming T. Liu
   Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:319-327 [Journal]
   
4. Mahadev Satyanarayanan, Ellen H. Siegel
   Parallel Communication in a Large Distributed Environment. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:329-348 [Journal]
   
5. Gurindar S. Sohi
   Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:349-359 [Journal]
   
6. Stanislaw J. Piestrak
   Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:360-374 [Journal]
   
7. Carsten Vogt
   A Buffer-Based Method for storage Allocation in an Object-Oriented System. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:375-383 [Journal]
   
8. Michael J. Quinn
   Analysis and Implementation of Branch-and Bound Algorithms on a Hypercube Multicomputer. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:384-387 [Journal]
   
9. Jien-Chung Lo, Suchai Thanawastien
   On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1990, v:39, n:3, pp:387-393 [Journal]
   
10. Wei-Ming Lin, Viktor K. Prasanna
    A Note on the Linear Transformation Method for Systolic Array Design. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:393-399 [Journal]
    
11. Sanjeev Saxena, P. C. P. Bhatt, V. C. Prasad
    Efficient VLSI Parallel Algorithm for Delaunay Triangulation on Orthogonal Tree Network in Two and Three Dimensions. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:400-404 [Journal]
    
12. Bong-Rad Choi, Kyu Ho Park, Myunghwan Kim
    An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:404-407 [Journal]
    
13. Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis
    An Efficient TSC 1-out-of-3 Code Checker. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:407-411 [Journal]
    
14. Sung Je Hong
    The Design of a Testable Parallel Multiplier. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1990, v:39, n:3, pp:411-416 [Journal]