Siamak Arya An Optimal Instruction-Scheduling Model for a Class of Vector Processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1985, v:34, n:11, pp:981-995 [Journal]
Nripendra N. Biswas On Bit Steering in the Minimization of the Control Memory of Microprogrammed Processors. [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1985, v:34, n:11, pp:1057-1061 [Journal]
John H. Wensley Further Comments on "The Reliability of Periodically Repaired n-1/n Parallel Redundant Systems". [Citation Graph (0, 0)][DBLP] IEEE Trans. Computers, 1985, v:34, n:11, pp:1068- [Journal]
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