Journals in DBLP

IEEE Trans. Computers
1994, volume: 43, number: 1

1. Yean-Shiang Leu, David Hung-Chang Du
   Cycle Compensation Protocol: A Fair Protocol for the Unidirectional Twin-Bus Architecture. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:1-12 [Journal]
   
2. Zevi Miller, Dan Pritikin, Ivan Hal Sudborough
   Near Embeddings of Hypercubes into Cayley Graphs on the Symmetric Group. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:13-22 [Journal]
   
3. Hsing-Lung Chen, Nian-Feng Tzeng
   Efficient Resource Placement in Hypercubes Using Multiple-Adjacency Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:23-33 [Journal]
   
4. Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi
   High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:34-42 [Journal]
   
5. Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu
   Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:43-51 [Journal]
   
6. Mark A. Holliday, Michael Stumm
   Performance Evaluation of Hierarchical Ring-Based Shared Memory Multiprocessors. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:52-67 [Journal]
   
7. Stanislaw J. Piestrak
   Design of Residue Generators and Multioperand Modular Adders Using Carry-Save Adders. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:68-77 [Journal]
   
8. Neil M. Wigley, Graham A. Jullien, Daniel Reaume
   Large Dynamic Range Computations over Small Finite Rings. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:78-86 [Journal]
   
9. Deng-Jyi Chen, Min-Sheng Lin
   On Distributed Computing Systems Reliability Analysis Under Program Execution Constraints. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 1994, v:43, n:1, pp:87-97 [Journal]
   
10. Younès Karkouri, El Mostapha Aboulhamid, Eduard Cerny, Alain Verreault
    Use of Fault Dropping for Multiple Fault Analysis. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:98-103 [Journal]
    
11. Keshab K. Parhi, Frank H. Wu, Kalyan Genesan
    Sequential and Parallel Neural Network Vector Quantizers. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:104-109 [Journal]
    
12. Prasant Mohapatra, Chita R. Das, Tse-Yun Feng
    Performance Analysis of Cluster-Based Multiprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:109-114 [Journal]
    
13. Francisco Corella
    Automated Verification of Behavioral Equivalence for Microprocessors. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:115-117 [Journal]
    
14. K. Vijayan Asari, C. Eswaran
    An Optimization Technique for the Design of Multiple Valued PLA's. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:118-122 [Journal]
    
15. Bapiraju Vinnakota, V. V. Bapeswara Rao
    Generation of All Reed-Muller Expansions of a Switching Function. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:122-124 [Journal]
    
16. Syed Masud Mahmud
    Comments on ``Synthetic Traces for Trace-Driven Simulation of Cache Memories''. [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:125-126 [Journal]
    
17. Mario Blaum, Jehoshua Bruck, Ludo M. G. M. Tolhuizen
    A Note on "A Systematic (12, 8) Code for Correcting Single Errors and Detecting Adjacent Errors". [Citation Graph (0, 0)][DBLP]
    IEEE Trans. Computers, 1994, v:43, n:1, pp:125- [Journal]