Journals in DBLP

IEEE Trans. Computers
2005, volume: 54, number: 1

1. Gam D. Nguyen
   Error-Detection Codes: Algorithms and Fast Implementation. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:1-11 [Journal]
   
2. Marcelo E. Kaihara, Naofumi Takagi
   A Hardware Algorithm for Modular Multiplication/Division. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:12-21 [Journal]
   
3. Alex Ramírez, Josep-Lluis Larriba-Pey, Mateo Valero
   Software Trace Cache. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:22-35 [Journal]
   
4. Harshavardhan Sabbineni, Krishnendu Chakrabarty
   Location-Aided Flooding: An Energy-Efficient Data Dissemination Protocol for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:36-46 [Journal]
   
5. Tei-Wei Kuo, Yung-Sheng Chao, Chin-Fu Kuo, Cheng Chang
   Real-Time Dwell Scheduling of Component-Oriented Phased Array Radars. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:47-60 [Journal]
   
6. Ismet Bayraktaroglu, Alex Orailoglu
   The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:61-75 [Journal]
   
7. Chidamber Kulkarni, C. Ghez, Miguel Miranda, Francky Catthoor, Hugo De Man
   Cache Conscious Data Layout Organization for Conflict Miss Reduction in Embedded Multimedia Applications. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:76-81 [Journal]
   
8. Peter G. Sassone, D. Scott Wills
   Scaling Up the Atlas Chip-Multiprocessor. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:82-87 [Journal]
   
9. Ganesan Umanesan, Eiji Fujiwara
   Parallel Decoding Cyclic Burst Error Correcting Codes. [Citation Graph (0, 0)][DBLP]
   IEEE Trans. Computers, 2005, v:54, n:1, pp:87-92 [Journal]